Solid-state drive (SSD) has gain prevalence in consumer and enterprise storage markets. However, its reliability is declining with the wearing of the Flash memory. The error correcting codes (ECCs) are generally applied in SSD to cope with bit errors caused by abrasion, however, the lifetime of pages in Flash is still limited to their fixed correctability. Due to different process and usage, the pages of Flash deteriorate in different speeds, which limited the service time of SSD. In order to prolong the lifetime of SSD, we proposed a Page Lifetime-aware Scrubbing (LaScrub) scheme to find dangerous pages which exist more bit errors. The simulation results show the proposed scheme is able to enhance the reliability of SSD. It gains 86% storage space compared with normal SSD at the same reliability requirement.
QR decomposition (QRD) has been a vital component for various baseband processing algorithms, and is one potential bottleneck for next generation (5G) high-performance MIMO systems. To ulteriorly optimize the processing latency (PL) of QRD hardware architecture, this letter proposes a novel anticipated MGS (AMGS) algorithm based on conventional MGS algorithm. Anticipated computing is proposed in AMGS to diminish the PL. Moreover, Reciprocal square root (RSR) algorithm is designed to eliminate the complex operations (dividing and square root), making AMGS algorithm suit more for baseband processors. To evaluate the performance of the proposed AMGS algorithm, the corresponding triangular systolic array (TSA) hardware architecture is also implemented based on AMGS algorithm, whose working frequency is up to 417 MHz in 0.13 um CMOS technology to decompose a 4 × 4 real matrix in 31 clock cycles. The implementation results show that the PL performance is superior to other similar works of the literatures we know.
Three dimensional Network-on-chip (3D NoC) is regarded as an attractive architecture delivering high communication performance. However, due to its high power density and strong vertical thermal correlation, thermal issues in 3D NoC are critical. In this paper, we propose a thermal-aware task mapping algorithm (3D-TTM) to reduce peak temperature meanwhile minimize the communication energy consumption. Experimental results show that the proposed scheme can achieve significant peak temperature reduction (up to 5.75 K) when compared to other methods. Moreover, our proposed algorithm achieves up to 63.34% communication energy consumption reduction.
In this paper, an original method is proposed to implement temperature compensation for a bandgap reference (BGR) circuit without any auxiliary circuits. By employing resistor combinations (formed by different type of resistors) with specified temperature coefficients (TC), the temperature coefficient of a previous reported bandgap reference is improved from 22.11 ppm/°C to 3.499 ppm/°C (−25°C–85°C). In order to accomplish the improvement, a useful model is also proposed to help understand the relationship among the TCs of resistors’ combinations and BGR.
A design method for a miniaturized small resonant aperture by modifying a ridge structure is presented, and its performance is verified experimentally. The proposed miniaturized aperture was designed by deforming the straight ridge structure of an H-shaped aperture with a two-step ridge of different lengths and widths, which resembles the capacitor symbol shape of the electric circuit. Experiment results show that the resonant frequency of the proposed aperture decreases from 5.06 GHz to 2.565 GHz (49.3%) compared to the conventional H-shaped aperture. Its transmission cross section increased by 3.78 times, and the aperture length-to-wavelength ratio is reduced to 0.09.
In this paper, an arbitrary phase-difference structure using short-circuit stubs and coupled-line with weak coupling is presented. Compared with conventional coupled-line phase shifters, the proposed coupled-line configuration covers a wide phase range over a broad band. The simulation exhibits a phase range from 15° to 180°. To verified the configuration, 90° and 180° phase shifters are fabricated and measured. According to the measurement results, both 90° and 180° phase shifters achieve bandwidths over 60% with in-band performance of return loss greater than 10 dB, insertion loss less than 1 dB, and phase deviation less than ±5°.
Multilevel inverter, a powerful electronic device capable of supplying desired alternating voltage level, is a renowned device majorly employed in appliances such as UPS systems, huge drives of induction motors as well as Transmission Systems. Multilevel inverters acquires the wanted output of their voltage from varied DC voltage sources. Thus, the number of DC voltage sources is directly proportional to the level of output voltage procured by the inverter. Multilevel inverters are constituted with several major advantages like, better harmonic performance, lower semiconductor voltage stress, lower Electro Magnetic Interference (EMI) and diminished losses on account of switching. However, in spite of these, their output voltage runs in accordance with the input from DC sources. Hence, to avoid such limitation there is requirement for an intermediate DC to DC converter in order to boost the working of the MLI output voltage. Thus, in accordance with the above limitation, a seven-level cascaded Z-source based multilevel inverter is proposed for this task. MATLAB/Simulink power system toolbox has been employed for the proposed system, in consequent of which experimental findings are analyzed to attest the efficiency of the method.
SVM-based granular resampling method is put forward to obtain a robust classification model for energy-efficient ECG systems. The classification model consists of a low-complexity model to filter most easy-to-learn heartbeats and a high-accuracy classifier to identify the remained heartbeats. Energy-efficient hardware architecture for multi-class heartbeat classification is implemented based on the classification model. The architecture optimizations include memory segmentation to reduce energy consumption and time domain reuse to save resources. We adopt 40-nm CMOS process to implement the proposed design. It provides an average prediction speedup by 57.21% and a significant energy dissipation reduction by 52.22% per classification compared with the design without low-complexity models.
This paper presents a multiband reconfigurable low noise amplifier (LNA) based on dual-feedback common-gate (CG) configuration. The input impedance of the LNA is tuned synchronously with output load due to the reflection of load impedance to input by the proposed source-follower positive feedback method. This method also improves the stability of the LNA, which is an issue in conventional positive feedback methods. In addition, both the source-follower positive feedback and the negative feedback by capacitor cross-coupling help to reduce noise figure. Fabricated in TSMC 0.18 µm CMOS process, measurement results show the LNA is reconfigurable from 1.833 GHz to 2.47 GHz, with S11 automatically centered with S21. It achieves a power gain from 15 to 17.4 dB, 1.62 dB minimum NF, and −4.4 dBm maximum IIP3. 10.5 mA current is consumed from 1.8 V supply.
The equivalent circuit of signal-ground through-silicon-via (GS-TSV) in slow wave region is developed based on the microwave theory, and is verified by employing ANSYS HFSS. The ADS results of the equivalent circuit of GS-TSV consistent well with the HFSS simulation data. The results of slow-wave equivalent circuit are more accurate than those of widely used quasi-transverse electric and magnetic (TEM) equivalent circuit in slow wave region.
This letter presents the implementation of a 6-bit true-time-delay (TTD) transmit/receive (T/R) module in X-band. Improved phase linearity is achieved by using thin film coplanar waveguide transmission lines than traditional microstrip lines or lumped LC components of the most other TTD designs. In order to meet the requirement of the large dynamic temperature range in practice, the hybrid coupler reflective phase shifters with varactor diodes are adopted in long-time-delay units as temperature compensations for thermal phase drift. Experimental results of this TTD T/R module are carried out within a bandwidth of 1.2 GHz at X-band. The gain flatness is better than 1 dB and RMSE of the phase errors is less than 7° in all the transmitting and receiving delay states.