This paper proposed a self-adaptive blanking time (SABT) circuit for fast IGBT de-saturation short-circuit detection. When IGBT normally turns on or experiences fault under load (FUL), the blanking time is implemented by detecting the variation of IGBT collector-to-emitter voltage VCE. While when IGBT is under hard switching failure (HSF), the blanking time is determined by detecting gate voltage VGE. The simulation with the UMC 0.6µm 700V technology indicates that the proposed SABT circuit can quickly detect FUL and HSF. Compared to the conventional blanking time circuit, the SABT circuit can shorten the fault detection time of FUL from 1.3µs to 35.3ns, while the fault detection time of HSF condition is reduced from 2.329µs to 294ns.
The fundamental active load-pull behavioral model, K-parameter, can be used to model the power amplifier (PA) quickly and accurately. When extracting the K-parameter model of a PA, both forward and reverse excitation signals are used in the same time for the PA to establish the large-signal operating point (LSOP). Because of system impedance mismatch and limited isolation of the couplers, the recorded signal is the product of the superposition of forward and reverse excitation vectors. To solve this problem, this paper proposes a data processing method to recover the true forward and reverse excitations on the PA’s ports, while introduces an extraction setup for broadband PA. Finally, a 2-6 GHz 3W PA is used for validation of proposed extraction method.
This paper proposes a novel maximum power point tracking (MPPT) algorithm that is combined with the advanced three-point weight comparison method (ATPWC) and MPPT limit detect (LD) mechanism and applied to a single stage standalone solar photovoltaic system. The boost converter is connected to the inverter and filter to deliver single-phase AC 110VAC/60Hz to the load. The MPPT LD detects when the system does not need MPPT based on the solar photovoltaic module’s (SPV module) Rpv and load Ro. In addition, this study performs actual measurements for validation, in which the proposed algorithm is used in the built single-stage standalone solar photovoltaic system and compared with the ATPWC, three-point weight comparison method (TPWC), and conventional perturbation and observation (P&O) for MPPT efficiency. The result shows that the proposed algorithm is better than the other three algorithms. When the system is under a heavy load (Rpv>Ro), the overall system efficiency is 80%, while the efficiency under a non-heavy load (Rpv≤Ro) is 99%.
This paper proposes an ultra-low power active diode (ADIO) using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. The proposed ADIO consists of a MOS switch and hysteresis common gate comparator, which eliminates unwanted ripple and noise voltages. The hysteresis comparator controls the MOS switch to turn ON or OFF, depending on the input and output voltages. The hysteresis voltages of the comparator can be controlled by the current flowing in the comparator. The measurement results demonstrated that the hysteresis comparator had -26 and 25 mV hysteresis voltages and the ADIO using the hysteresis comparator eliminated unwanted ripple voltage. The maximum current consumption of our ADIO was 11.8 nA.
This paper presents an ultra-low-voltage (ULV) high-resolution low-power continuous-time delta-sigma modulator for implantable biomedical devices. The 2nd-order single-bit modulator adopts feed-forward architecture and a new fully differential ULV amplifier to achieve high signal-to-noise plus distortion ratio (SNDR) and power-efficient operation under 0.4-V supply. The amplifier employs a gate-body-input class-AB output topology with a local common-mode-feedback (CMFB) loop to achieve large output swing for less harmonic distortion with low power consumption. A robust clock generator is adopted to ensure modulator’s consistent performances across ±10% power supply variation. The modulator is fabricated in a 130-nm CMOS technology with regular VT transistors. The measurement results show that the modulator achieves 75.5-dB SNDR and consumes 6.6-µW under nominal 0.4-V supply within a 500-Hz bandwidth. The achieved SNDR is the best one among the recent reported DSMs operating at 0.4V or below for implantable biomedical applications. The modulator also achieves a 69dB SNDR with 3.7-µW power consumption even operating at 0.32V supply.
This letter presents the self-referenced architecture to simplify design process and current mirror based power stage with wide input voltage to expand the application range of low-dropout (LDO) regulator. Featuring a BiCMOS symmetrical operational transconductance amplifier (OTA) whose input and power supply are also the output of LDO, the LDO itself is a voltage reference as well as a voltage regulator. Improved phase lead compensation is applied with much smaller compensation capacitor, and enhanced current mirror (ECM) buffer is introduced. Experimental results of the proposed LDO in a 0.18 µm BCD process verified this self-referenced structure. The measured maximum input voltage is 12 V and the power supply rejection (PSR) is -40 dB at 50 KHz. The line regulation is 0.34 mV/V and total quiescent current is about 8.2 µA at light load.
This paper describes terahertz (THz)-wave generation within forbidden bands in polar crystals, focusing on the A1 phonon modes in lithium niobate. This material exhibits two negative-permittivity frequency ranges at 7.4-12.7 THz and 18.8-25.6 THz for the lowest and highest A1 modes, respectively. Exploiting the finite-difference time-domain simulations, we demonstrate that both the surface phonon modes can be radiative with a structured grating. Fourier analyses of the radiative fields reveal the relevant peaks in the spectrum as well as the dispersion relations. Our results provide a novel method for coherent THz-wave sources at unexplored THz frequencies.
In this paper, a slot array in 5G communication band is proposed. The pattern function is first modified and calculated. Then, the array is constructed using rectangular waveguides. Based on our simulated and measured results, the proposed method has successfully achieved the slot arrays with low side lobes and high gain. The proposed antenna arrays can be applied in modern 5G communication systems.
Explorers attempting to land on a lunar or planetary surface must use three-dimensional image sensors to measure landing site topography for obstacle avoidance. Requirements for such sensors are similar to those mounted on vehicles and include the need for time synchronization within one frame. We introduce a 1K (32 × 32)-pixel three-dimensional image sensor using an array of InGaAs Geiger-mode avalanche photodiodes capable of photon counting in eye-safe bands and present evaluation results for sensitivity and resolution.
This paper presents a method to extend the back-off range of an asymmetric Doherty power amplifier (DPA) to 12dB using a reactive output impedance of the peaking amplifier. An analytical method is employed to determine the desired reactive output impedance for specific output power back-off (OPBO) range. Then, a peaking output matching network is designed to achieve the desired impedance to enlarge the efficiency of the carrier amplifier. When compared with conventional design, the OPBO range can be improved by about 2dB using the proposed method. For verification, a 3.4-3.6GHz asymmetric DPA with enhanced OPBO range was designed using 10 and 30W GaN HEMT transistors. The measured efficiencies of 47%-49% at 12dB back-off and 63%-66% at saturation are obtained over the whole frequency range. For a 40MHz LTE signal at 3.5GHz, the adjacent channel leakage ratio is -50dBc after linearization with an average efficiency of higher than 50%.
A low power, fine resolution and good linearity time-to-digital converter (TDC) for All digital phase-locked loops is presented. The proposed two-step TDC consists of coarse-TDC (CTDC), Coarse-Fine Interface and fine-TDC (FTDC). The CTDC adopts Set-Reset-based arbiters and signal tracking mechanism to reduce power consumption. FTDC employs Vernier delay-line to obtain fine resolution. The linear delay-line structure of CTDC and FTDC and Coarse-Fine Interface’s dynamic logic gate both contribute to good linearity. Implemented in 180nm CMOS process, the TDC achieves 6.2ps resolution and 8bits range. It consumes only 520µW and achieves the best figure-of-merit (FoM) compared with other state-of-the-art TDCs.
This letter proposes a MOS-current-mode-logic (MCML) driver with an active inductor structure to provide large voltage swing with linear response. This design is implemented in 45 nm CMOS with 1.2V supply. Compared with conventional active-inductor-based circuits, this topology enlarges the available single-ended output voltage swing from less than 350 mV to 600 mV. The MCML driver occupies a chip area of 0.0264 mm2. Operating at 10 Gb/s over a channel with 3.5 dB loss at 5 GHz, the eye height is measured as 351 mV with 600 mV single-ended voltage swing, and the peak-to-peak jitter is 14.9 ps (0.149 UI).
This letter presents a reconfigurable dual-band power amplifier based on memristor. The memristor is first applied in the field of RF power amplifier design. Based on the basic theory of memristor, different values of the resistance of the memristor are obtained by adding different dc voltages on the memristor, and conversion between different output matching circuits is realized. Thus, a reconfigurable output matching circuit is constructed to realize a reconfigurable dual-band power amplifier. To verify the effectiveness of the proposed method, a reconfigurable dual-band power amplifier is designed and simulated. The simulation results show that by setting different dc voltages of the memristor, the saturated output power of 41dBm and drain efficiency of more than 70% can be achieved at two frequency points of 2.0GHz and 3.0GHz, and the gain can reach 10dB.