The malicious attacks adversely affect every user over the Internet. This paper proposes an application-specific integrated circuit (ASIC) design with parallel exact matching (PEM) architecture to accelerate the Snort intrusion detection system (IDS). The PEM is half mesh architecture to compare the Snort rules in parallel. The ASIC named snort rule accelerator (SRA) focuses on the TCP protocol to detect the attacks of e-mail and web applications. As shown in post-layout simulation, the ASIC operated at 435 MHz to perform the needs of high speed with 13.9 Gbps system throughputs. So that it resolves the complexity of information security limitation to manage data received from the 10 Gbps core network.

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This paper presents an ultra-low-voltage high-efficiency interface circuit for energy harvesting, which features self-powered design and digital switch control. The proposed rectifier includes bridge rectifier and active diode. The former introduces self-driven switches and ultra-low voltage divider to reduce the voltage drop for wide output voltage swing. The latter adopts a common-gate comparator as switch control block to output a nearly digital signal, thereby improving dynamic response and anti-noise ability. The entire circuit exhibits good conversion efficiency and stability. Its minimum input voltage is down to 225 mV. The maximum voltage efficiency reaches to 96.3%, supplying the output current of 29 µA and the output power of 15.43 µW. The maximum power efficiency is 96.5%, providing the output current of over 16.1 µA and the output power of 5.19 µW. The whole circuit consumes the power loss of 1.42 µW.

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Boron-doped amorphous carbon (a-C:B) films were successfully synthesized via a bias-assisted pyrolysis-chemical vapor deposition (CVD). The effect of substrate bias on the thickness, surface morphology, electrical properties of a-C:B film were investigated. The AFM measurements and conductivity result show the surface roughness and resistivity of a-C:B films decreases with increasing substrate bias from 0 to −20 V. The fabricated films were evaluated for use in photovoltaic solar cells. The fabricated solar cell with the configuration of Au/p-C:B/n-Si/Au achieved conversion efficiency (η) of 1.431% at applied bias voltage of −20 V. This result showed the successful interstitial doping of boron in the amorphous carbon films deposited by this method.

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The low-rate speech quality evaluation has an obvious error for the uncertain factors with multi-source, heterogeneous and time-varying. This paper proposed a new model to measure the error of the speech quality evaluation based on entropy (SQEE). The gray correlation analysis among the factors but also the uncertain entropy was designed to keep the model optimization and equivalence. What’s more, the parameters of determinacy and sensitivity were proposed to measure the accuracy and the efficiency. After the theory and simulation, the new method enhanced the error of the traditional methods (PESQ, PQSM) about 30% below the 250 ms-delay.

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A Physical Unclonable Function (PUF) can be used to provide authentication of devices by producing die-unique responses. In PUFs based on ring oscillators (ROs) the responses are derived from the oscillation frequencies of the ROs. However, RO PUFs can be vulnerable to attack due to the frequency distribution characteristics of the RO arrays. In this letter, in order to improve the design of RO PUFs for FPGA devices, the frequencies of RO arrays implemented on a large number of FPGA chips are statistically analyzed. Three RO frequency distribution (ROFD) characteristics, which can be used to improve the design of RO PUFs are observed and discussed.

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In the conventional second order, single bit, discrete ΔΣ Modulator (DSM), the sampling of input signal and DSM operation is performed at the same frequency. In this conventional DSM, signal to noise ratio (SNR) starts falling down rapidly when the modulus of normalized input signal is above 0.47. The integrators output become arbitrarily large which make the system unstable by saturating the operational amplifiers used in the circuit. There are recent papers in which the modulus of normalized input signal can be increased up to 0.7. In the present paper, a second order DSM with different sampling frequency and DSM clock frequency is proposed. The operating period of the proposed DSM is proportional to the sampled analog input signal. The proposed DSM can operate for the full range of normalized input signal (−1 to +1), has better signal to noise ratio (SNR) in the higher range and can be realized using cmos circuit of supply voltage ±1.5 V. The maximum bound on the integrators outputs is 1.5 V. The proposed DSM has unidirectional output and the oscillation at the output for zero input is no longer present and these properties are essential to drive stepper motors which are the actuators for control valves in industry. In the output spectrum near the signal frequency, the noise level is well below the signal level. The proposed DSM results in low power, stable full range operation with better SNR and power spectral density (PSD).

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We derive a time-domain (TD) asymptotic-numerical solution for the transient scattered electric field by a coated conducting cylinder covered with a thin lossy dielectric material by substituting the frequency-domain asymptotic solution into the transient scattered electric field integral. The TD asymptotic-numerical solution is represented by a combination of each transient scattered field element which is obtained from the numerical integration. The validity and computational efficiency of the TD asymptotic-numerical solution are confirmed by comparing with the reference solution. We show that, since the TD asymptotic-numerical solution can extract and observe each pulse wave element from the response waveform even when the pulse wave elements overlap mutually, it is effective understanding the scattering phenomena in detail.

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This paper studies rectifier circuits for RF energy harvesting based on Dickson charge pump. The best configuration of rectifiers is found that the body terminals of FETs are connected to their drains. Its performance is particularly superior when the load resistance is relatively higher. We also studied some derivative circuits, where the gate terminals are connected not to the own drains but the drains of the second neighbor FETs. In addition to this, we propose a new design guideline for determining the optimal rectifier parameters based on the output voltage universal curve. It helps us to find the optimum rectifier design parameters depending on the specification of the application targets.

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This letter presents a 529 GHz 2:1 dynamic frequency divider in a 130 nm InP HBT process, which, to the best of authors’ knowledge, is the fastest frequency divider reported thus far. The presented divider is based on a novel structure to overcome bandwidth limitations of traditional dynamic frequency divider design. On-wafer measurement shows that the divider operates with the input frequency from 528.0 GHz to 529.2 GHz with bias voltage tuning, while consuming P_DC ≤ 196 mW. A driver amplifier, integrated for testing purpose, dissipates 348 mW of dc power.

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Near-threshold-voltage (NTV) circuit is to set the operating voltage near the threshold voltage of CMOS transistors to pursue the maximum energy efficiency. However, the characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. In this paper, we proposed a new dynamic-static hybrid near threshold voltage adder design. The proposed keeper design can suppress the leakage current and avoid signal contention in the dynamic CMOS circuit, which lets the dynamic CMOS logic family can be adapted to NTV environment with excellent speed characteristics and higher energy efficiency. The proposed low leakage dynamic-static hybrid NTV 32-bits adder design can achieve the maximum energy efficiency with 161.7% enhancement as compared to the mirror adder under NTV with 0.3 V.

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A passive mixer with a complementary gm stage and a low voltage IF trans-impedance amplifier, which can operate under low voltage conditions, is proposed in this letter. With at most two transistors stacked between vdd and gnd, the proposed mixer can be realized in regular CMOS processes without reducing the threshold voltage of transistors. A high conversion gain is obtained thanks to the high utilization efficiency of the RF current generated by the trans-conductance (gm) stage. A prototype of the proposed mixer structure which works in the frequency band from 1 GHz to 2 GHz is designed and fabricated in SMIC 65 nm CMOS process. Measurement results indicate that, the prototype achieves a conversion of 22 dB and a noise figure of 15 dB. The power consumption is 1.2 mW under the supply voltage of 0.6 V.

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Energy use is currently an important issue in mobile embedded systems, and this will be continue in the future because of battery problems. We focused on a Dynamic Voltage Frequency Scaling (DVFS) algorithm to save as much energy as possible, and investigated the correlation of operations between memory and CPU. We introduce an Operational Intensity (OI)-based DVFS algorithm to follow the optimal frequency to conserve energy in embedded systems. Our proposed method was verified using FPMark of EEMBC, and conserved energy up to 17% in a memory-bound application.

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We proposed and fabricated resonant-tunneling-diode (RTD) terahertz (THz) oscillators with a structure for high-frequency direct modulation, which is useful for high-capacity THz wireless communications. The oscillator is composed of RTD and slot antenna. To obtain high cut-off frequency of direct modulation, the capacitance of the metal-insulator-metal (MIM) layer forming the slot antenna was reduced without decrease in THz output power which was a problem in the previous structure. A cut-off frequency of 30 GHz was obtained in direct intensity modulation of the device oscillating at 350 GHz with the reduced MIM capacitance of 0.7 pF.

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Currently, the frequency ramp rate of most commercial direct digital synthesizer (DDS) chips is not more than several hundred MHz. In some communication or radar applications, the frequency ramp rate must reach several GHz. In order to greatly increase the frequency ramp rate, this paper proposes a full-custom multi-core & single-channel DDS (MCSC-DDS). This MCSC-DDS consists of some DDS sub-cores which are implemented in a field programmable gate array (FPGA) and a high speed digital analog converter (DAC) whose sampling frequency achieves several GHz. In FPGA, these DDS sub-cores operate in parallel to equivalent achieve ultra-high frequency ramp rate which is equal to the sampling frequency of the DAC. As an example, a compact and portable MCSC-DDS whose frequency ramp rate achieves 2.5 GHz is presented. It is mainly made up of a Virtex-5 FPGA and an AD9739. The measured chirp waveform has a maximum 2.5 GHz frequency ramp rate which demonstrates the efficiency of the MCSC-DDS.

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In this work, Wuhan University has proposed a vehicle mounted HF smart antenna system, which is used for anti-interference communication. Compared with existing work, the novelty of this work is as follows: 1. Propose a IF-based DBF hardware architecture, which has better stability and is easier to achieve channel expansion; 2. Verify the performance and limitation of existing superdirective beamforming method via field tests. 3. Propose and verify an effective anti-interference method by nulling technology. The experimental results prove that the system has good anti-interference performance.

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70-nm T-gate InP-based low noise In_0.52Al_0.48As/In_0.65Ga_0.35As pseudomorphic high electron mobility transistor (PHEMT) with well-balanced cutoff frequency f_t and maximum oscillation frequency f_max were designed and fabricated. DC, RF, and noise characterizations are demonstrated. The maximum saturation current density I_dss and maximum extrinsic transconductance g_m,max are measured to be 894 mA/mm and 1640 mS/mm, respectively. And the extrapolated f_t and f_max based on inflection point were 247 GHz and 392 GHz, respectively. Due to the disadvantages of traditionally used Y-factor method, the new cold-source method was adopted to measure the noise parameters. The minimum noise figure (NF_min) is 1 dB at 30 GHz associated with a gain of 15 dB at V_ds of 0.8 V and I_ds of 17 mA. These excellent results make this InP-based PHEMT one of the most suitable devices for millimeter wave low noise applications.

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This article was retracted. Please see retracted notification.

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As the Network-on-Chip (NoC) induces significant hardware overheads, it becomes the performance and scalability bottleneck of System-on-Chip (SoC) design. To address this challenge, we propose a multi-layer, non-blocking ring NoC architecture. Multi-layer links with different bandwidth achieve high link utilization and avoid protocol-level deadlock. The non-blocking architecture leverages bufferless router to reduce hardware overheads and simplifies router pipeline to reduce zero-load latency. We also propose a scalable global signal control mechanism to eliminate the starvation and avoid the loss of packets. Compared with the conventional ring network composed of dateline routers (DRing) and Intel Nehalem-EX ring network (NRing), our design achieves 69.4% and 12.3% performance improvements, respectively. Compared with DRing, it also reduces hardware overheads.

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We demonstrate an accurate remote measurement of heartbeats using an ultra-wideband radar system. Although most conventional systems use either continuous waves or impulse-radio systems for remote vital monitoring, continuous waves suffer from non-stationary clutters, while impulse-radio systems cannot detect heartbeats. Our ultra-wideband radar system has a moderate fractional bandwidth intermediate of these systems, resulting in both the suppression of clutters and high sensitivity in measuring accurate heart rates even in a dynamic environment. A simultaneous measurement of the vital signal of a participant employing the ultra-wideband radar and electrocardiography reveals the high accuracy of the radar system in measuring the heart rate varying over time.

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