Aiming at the problems of high complexity and large calculation quantity in the existing digital control strategies for single-inductor dual-output (SIDO) converter, this paper proposes a simple and reliable digital compensation control technology to suppress the cross-regulation. The design of the compensation control is only related to the selected circuit topology, thus it will not be redesigned for different control strategies. Taking the digital predictive current-mode (DPC) controlled SIDO buck converter as an example, the small signal model is firstly established. Based on these transfer functions, the theory of the proposed digital compensation method, which can suppress cross-regulation is analyzed. In the meanwhile, the digital control algorithm is derived. Simulation and experimental results verify the correctness of the theoretical analysis.

A new sliding mode speed controller (NSMC) based on an improved genetic algorithm (IGA) is proposed to solve the problems of disturbance rejection and response speed differences in traditional vector control of permanent magnet synchronous motor (PMSM) driver systems. The improved algorithm adopts an adaptive crossover and mutation probability formula, which enhances the global search ability of the genetic algorithm. The algorithm is used to optimize the parameters of the sliding mode speed controller. Moreover, the sliding mode disturbance observer is used to generate feedforward signals to compensate for the influence of external disturbances. It is applied to the speed control loop to effectively improve the system’s robustness. Finally, numerical simulation results demonstrate the robustness and fast response of the proposed method.

In this letter, a 30MHz-3GHz 10W single pole double throw (SPDT) switch with 3.3V low supply voltage fabricated in 0.5um GaAs pHEMT technology process is presented. A feedforward capacitor pair is introduced in each stacked FET, which makes full use of the advantages of high breakdown voltage (V_BDG) of GaAs process under low supply voltage and enhances the power handling of each FET unit. Under specific power level, switch with reduced number of stacked FETs and low insertion loss are achieved. Meanwhile, uniform-partial-voltage stacked FET units with different gate width is applied to the switch design, which solves the problem of non-uniform partial voltage caused by parasitic capacitance (C_pd) between stacked FETs. As a result, the power handling of the switch is higher than 40dBm under continuous wave. Besides, the switch designed in this letter achieves 0.5dB insertion loss at 1.5GHz and the input and output return loss is less than -18dB at the whole frequency band. The test results verify the accuracy of the theoretical analysis.

This paper presents a 12-bit 2.32GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175mW.

This paper presents a lowpass filter for 5.8GHz Doppler radar with an intermediate frequency signal hold function, which significantly reduces system power by interrupt mode operation. Additionally, it proposes a novel complementary push-pull DC offset calibration method to calibrate the DC voltage of the lowpass filter with the common mode voltage. Compared to traditional methods, the proposed scheme effectively stabilize the quiescent operating point of the receiver. The experimental results show that the power consumption of the proposed filter is 0.019mW, calibrated DC voltage is 1.65V, and residual DC voltage is less than 1mV.

The previous PLC E₃₁ and E₁₃ mode converters employ linear tapered structures to fulfill the adiabatic coupling condition and achieve a high mode conversion efficiency, which requires long taper lengths. In this paper, we propose two types of PLC tapered structures that can be applied in different scenarios using fast quasiadiabatic dynamics. These structures enable mode conversions of E₃₁-E₁₃ modes, as well as E₃₁-LP₀₂ and E₁₃-LP_21b modes, respectively. The E₃₁-E₁₃ mode converter can be reduced from the previous three-stage linear taper of 12000 µm to approximately 4000 µm in length. Similarly, the E₃₁-LP₀₂, E₁₃-LP_21b mode converter can be reduced from the previous two-stage linear taper of over 6000 µm to approximately 4000 µm in length.

This brief introduces an area-efficient AdderNet hardware accelerator. AdderNet replaces multiply-accumulate computations of neural network processing with addition operations, thereby reducing computational cost. However, the previous accelerator uses two adders for a kernel computation to implement an absolute value computation, which still has circuit redundancy. For the efficient AdderNet acceleration, we propose a reconfigurable kernel unit and merged adder tree structure to relax such a computational circuit overhead. The proposed merged adder tree reduces the computing area by 23-28% compared to the state-of-the-art AdderNet hardware architecture.

In this letter, a second harmonic suppressed millimeter-wave (mm-wave) gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) power amplifier (PA) using the self-resonate characteristic of the capacitor is proposed. Based on a simple modified band-pass output matching network, a novel second harmonic suppression method by utilizing the self-resonate characteristic of the on-chip capacitor is proposed, which can realize the harmonic suppression without any additional tuning structures. For verification, a 24-to-28-GHz GaN MMIC PA was designed using a 150-nm GaN on silicon carbide high electron mobility transistor process. The fabricated PA achieved a saturated power range of 32.5-34dBm, with a corresponding power-added efficiency (PAE) of 37.5%-44.5%. The amplifier achieved good linearity when excited by a 400-MHz orthogonal frequency division multiplexing signal after applying digital predistortion.

A low phase noise low power ring voltage-controlled oscillator (Ring-VCO) is proposed for phase-locked loops (PLLs) in the 802.11ah communication protocol band. A three-stage Ring-VCO with dual-path structure delay cells is designed to meet the high performance requirements of Internet of Things. The main noise source in the differential delay cell can be eliminated at the differential output, thus reducing phase noise. Implemented in an old TSMC 0.18µm CMOS process, the Ring-VCO achieves a tuning range of 343.56-974.56MHz. The phase noise at 1MHz offset varies from -116.28 to -108.74dBc/Hz, and the current consumed is 2.27mA.

As autonomous driving technology advances, the requirements for object detection are becoming increasingly high. Non-maximum suppression (NMS) algorithm, as a key component in traffic object detection algorithms, is an independent post-processing process in the object detection framework. Due to the complexity of real-world road scenarios and high density of detected entities in urban traffic, the number of candidate bounding boxes generated by the neural network is large. Hence, low-precision processors may generate a significant number of redundant target bounding boxes. The excessive output of redundant target bounding boxes not only imposes a workload on subsequent processing but also has the potential to result in non-optimal decision-making. We propose a high-performance NMS processor that can quickly process a large number of candidate boxes without performing sorting of their scores. Also, it has low precision loss computing units and high parallel computing arrays. Combined with algorithm design, it effectively reduces the computational complexity and reduces the inference time of the end-to-end task of the NMS algorithm. Thus, our NMS processor’s speed is comparable to SOTA architecture, and the average accuracy loss is only 0.4%.

This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delay-product of the proposed SAFF shows 3.0× improvement compared with the conventional SAFF.

This study focuses on the improvement of the performance of high-frequency current transformer (HFCT) for Partial Discharge Measurement and thus reveals a new design method of HFCT. An annular nickel-zinc ferrite is used as the magnetic core of the HFCT, and the parameters such as the number of winding turns and the diameter of the enameled wire are optimized. To test the HFCT, an experimental test platform is built according to the technical specifications of high-frequency partial discharge charged detection equipment. The test contents of the HFCT include transmission impedance, sensitivity, anti-interference characteristics, etc. The test results show that the new HFCT has a good response performance from 1MHz to 25MHz, the maximum transmission impedance value can reach 16.4mV/mA, the apparent charge of 5pC can be measured and signal-to-noise ratio is greater than 2:1. In addition, the designed HFCT also has good anti-interference and stability. With the self-designed low-power portable high-voltage cable insulation tester (mainly including signal conditioning circuit and data acquisition circuit), in the high-voltage laboratory, built a simulated discharge experimental circuit on the plate-pin, ball-ball two discharge models for high-voltage testing, the use of the developed HFCT to detect the partial discharge of the insulating polyethylene medium. The test results show that the HFCT can detect the partial discharge pulse signals before breakdown, with accurate data and reliable performance.

This letter presents a new microstrip diplexer with self-packaged and wide bandwidth based on substrate-integrated suspended line (SISL) technology. Diplexer consists of D-CRLH filters which include mixed coupling. The electromagnetic interaction is canceled out in the filter, generating two transmission zeros and giving the filter good stopband suppression. Diplexer utilizes a T-junction to make filters work in parallel. Each channel filter can be individually controlled. To validate the proposal, a diplexer operating at 1.88GHz and 2.64GHz with fractional bandwidth (FBW) of 14.6% and 19.1% is designed and fabricated. A good agreement is perceived between measured and simulated.