A tunable transformer-based directional coupler for UHF RFID readers is presented. Based on the current cancellation between inductively and capacitively coupled power through a non-inverting transformer and two coupling capacitors, respectively, the proposed directional coupler exhibits high isolation performance. In addition, by a tuning capacitor array and a terminal resistor array, the notch frequency of the coupler is tunable over the global UHF RFID band. The coupler is fabricated in a SMIC 0.18-µm CMOS process and the measured isolation is better than −60-dB from 840 MHz to 960 MHz. Besides, the transmission loss and the coupling factor at the notch frequency vary from −0.86-dB to −0.7-dB and from −16.2-dB to −15.3-dB, respectively.

The power loss modeling is a key procedure during designing the converter, especially in high temperature operation. This letter presents a practical method for predicting the temperature-related power losses for buck converter. In order to build the loss model, the datasheet driven method is adopted which requires only the information in device datasheets. The accuracy of the proposed model is demonstrated by the experiment. Experimental results are consistent with the theoretical analysis over the entire temperature range.

In the construction of polar code, the selection of frozen bits affects the error-correcting performance significantly. Several calculation-based algorithms have been proposed for general binary-input discrete memoryless channels (B-DMCs) like the additive white Gaussian noise (AWGN) channel. In this paper, a method for frozen bits selection based on Monte Carlo simulation and belief propagation (BP) decoding is proposed. The information bits are selected out one by one incrementally. The numerical results show that the proposed algorithm can effectively improve the bit error rate (BER) and frame error rate (FER) performance compared with the conventional selection method, especially in high signal noise ratio (SNR) region. Moreover, the algorithm can be used to construct polar codes with any rate through a complete iteration.

An optimized reference current detection method based on synchronous reference frame transformation and sliding discrete Fourier transform (SDFT) is proposed. The proposed method can be used to extract characteristic harmonic currents as the reference current of system from the load currents by fewer sampling points, meanwhile, the numbers of harmonics need to be calculated will reduce to half of traditional method, it means that the proposed method can reduce the computational effort and easy to engineering implementation, while achieving better dynamic performance compared with other methods. The results of simulation and experiment show the validity of this method.

We investigate experimentally the mutual synchronization of oscillating pulse edges developed in dissipatively point-coupled transmission lines periodically loaded with tunnel diodes (TDs). Based on the phase-reduction scheme, the mutually synchronized edges are shown to pass simultaneously the connected points. It then becomes possible to design the phase difference between synchronized edges by the arrangement of connected points. Using test TD lines fabricated on breadboards, the fundamental properties of mutually synchronized edges are successfully validated.

To obtain high accuracy, CMOS temperature sensors need to be calibrated. The current available calibration techniques are manual ones. They are time-consuming and expensive. They are not suitable for chip mass production. To solve the problem, we present an individual and automatic calibration technique for BJT-based CMOS temperature sensors. It is an automatic voltage calibration using the trimming circuit based on the successive-approximation algorithm. Experimental results show that after a 2-second auto-calibration, the sensor can achieve an accuracy of −1 °C∼1.5 °C from −40 °C to 100 °C.

A voltage-mode ultra low power four quadrant analog multiplier using subthreshold PMOS is presented in this paper. PMOS substract cell and combiner cell operating in the subthreshold region are used to lower the voltage-mode multiplier power consumption. Simulation results of the multiplier demonstrate a linearity error of 0.8%, a maximum THD of 4%, a −3 dB bandwidth of 1.4 MHz, and a power consumption of 77 nW with 100 fF load capacitor at a supply voltage of 0.6 V using a TSMC 0.18 um CMOS process.

In this paper, a computational intelligence method to model lossy substrate integrated waveguide (SIW) cavity resonators, the Neural Network Residual Kriging (NNRK) approach, is presented. Numerical results for the fundamental resonant frequency f_r and related quality factor Q_r computed for the case of lossy hexagonal SIW resonators demonstrate the NNRK superior estimation accuracy compared to that provided by the conventional Artificial Neural Networks (ANNs) models for these devices.

In this letter, an ultra-wideband (UWB) bandpass filter (BPF) based on CPW-to-microstrip transition structure is proposed. To improve its selectivity, an interdigital coupled-line and split ring resonator (SRR) are used to generate two extra transmission zeros located at the lower and upper edge of the passband separately. The measured results show that the proposed filter possesses satisfactory performance such as compact size, sharp roll-off, and wide fractional bandwidth of 133% (2.35–11.75 GHz). Moreover, a notched band with deep attenuation introduced by coupling T-shaped short stub (CTSSS) is achieved to block the ITU8.0 band with centre frequency of 8.2 GHz. And the notched band is controllable. This filter can be a good candidate for ultra-wideband applications.

This paper proposes a novel coarse-grained reconfigurable array (CGRA) with hierarchical context cache structure and efficient cache management approaches, including time-frequency weighted (TFW) context cache replacement strategy and context multi-casting (CMC) mechanism. By fully exploiting inherent configuration features, the configuration performance is improved by 18.2% with half context memory cost. Our CGRA was implemented under the process of TSMC 65 nm, which can work at the frequency of 200 MHz with the area of 23.2 mm². Compared to the previous CGRAs, our work has the advantage of 3.8∼12× performance improvement and 2.3∼15.7× energy efficiency increase.

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. The proposed pipeline-ΔΣ TDC is based on two-stage time quantization with pulse-train time amplifiers. It achieves an SNDR of 80 dB and a high resolution up to 0.23 ps. A MASH 1-1-1 ΔΣ modulator based on vernier lines is used to achieve third-order noise shaping. The proposed ADPLL has been implemented in a 0.13-µm CMOS technology. The measurement results show a 12-mW total power consumption. The in-band and out-band phase noise are −91 dBc/Hz@10 kHz and −128 dBc/Hz@1 MHz, respectively. The RMS jitter and peak-peak jitter are 2.9 ps and 21.5 ps, respectively.

Power efficient optical serial-to-parallel conversion is proposed using a linear technique based on Fractional OFDM scheme. A Fractional OFDM can mediate between N-OTDM and OFDM without any nonlinear signal processing and it is expected to incorporate both benefits of the densest serial and parallel features of N-OTDM and OFDM as well as power efficiency of a linear technique. The preliminary operation of serial-to-parallel conversion is verified so that a 10 GHz sine wave serial signal could be optically sampled by triple Nyquist pulses and be converted to three parallel intensity modulated signals at three Fr-OFDM channels.

We demonstrate a compact and low-loss liquid crystal loaded Si wired Mach-Zehnder (MZ) optical switch in the in-plane switching mode. The device is configured with a simple structured MZ interferometer in which one side of phase-shifter-electrodes is placed on the MZ-island-like area. A device with a 100-µm-long phase shifter has small footprint of within 300 × 80 µm² and exhibits quite low device losses and relatively smooth spectra with a voltage-length product of ∼0.4 V·mm. The thermal characteristics of the device are also evaluated and the device is found to be operable until at least 60°C.

In this paper, a fast relocation method is proposed, implemented and evaluated in a DSP/FPGA based GPS/SINS/CSAC deep integration hardware prototype. For the GPS receiver, when signal appears after the signal blockage or signal interference, the precise time information based on the reference of the CSAC and the position information from the SINS combined with the ephemeris can be used to calculate the frame counts and aid the realization of the fast relocation. A field test is conducted to verify and evaluate the performance of the algorithm. The results demonstrate that the proposed fast relocation algorithm can largely reduce the receiver relocation time. The result shows the relocation can be realized during 1 second while the traditional receiver usually needs at least 6 seconds for the relocation after the signal blockage.