This paper presents a new technique for parametric macro-modeling of tabulated S parameter data in frequency domain. The traditional technique is modified in such a way that barycentric interpolation is performed at residues of root models, rather than the whole root models. It avoids increasing the number of poles which represents the model complexity and makes the parametric macro-model more compact. An illustrative example involving a low-pass filter is presented for validation of the proposed method.
The pixels in the conventional image sensors are placed at lattice positions, and this causes the jaggies at the edge of the slant line we perceive, which is hard to resolve by pixel size reduction. The author has been proposing the method of reducing the jaggies effect by arranging the photo diode at pseudorandom positions, with keeping the lattice arrangement of pixel boundaries that are compatible with the conventional image sensor architecture. In this paper, the author discusses the design of CMOS image sensor with pseudorandom pixel placement, as well as the preliminary evaluation of the fabricated CMOS image sensor.
The electro-static discharging (ESD) gun test method is widely used and admitted for systems, but it will also bring some unwished factors to influence the accuracy and stability such as radiated electromagnetic (EM) and the unstable hand-held operational approach. In order to avoid the above factors, a traditional work uses a modified transmission line pulse (TLP) tester to deliver the IEC 61000-4-2 stress. However, the modification and recovery process of a TLP tester is complicated in addition to the potential damaging risks. Thus, this work proposes a novel TLP-based method to generate the IEC stress by adding an extra circuit network outside the TLP tester. Further, the proposed method with no need for internally modifying a TLP tester can efficiently solve the above issues.
A low noise and highly linear up-conversion digital TV (DTV) receiver front-end, which consists of a noise canceling body-driven pMOS common gate (CG) LNA, a LC-loaded passive mixer, and a surface acoustic wave (SAW) driver, is implemented in a 0.18 µm CMOS process. The pMOS input stage and body-driven technique in the conventional noise canceling capacitively cross-coupled (CCC) CG LNA greatly improve noise figure (NF) over DTV frequency band without extra power consumption. The linearity of the proposed up-conversion LC-loaded passive mixer and modified source follower-based SAW driver is high enough to handle strong blockers without suffering from desensitization. The designed RF front-end shows a measured conversion gain of greater than 17 dB, a NF of less than 2.7 dB, and a third-order input-referred intercept point (IIP3) of greater than −2.7 dBm over DTV frequency band. The power consumption of the proposed RF front-end is 70 mW at a 1.8 V supply voltage.
Three dimensional (3D) networks-on-chip (NoCs) is beneficial to performance improvement, but suffers severe thermal issues. Because of the fast packet switching activity and small area, an NoC router might even show higher power density than a process element, quite easily forming a thermal hotspot. Throttling based dynamic thermal managements (DTMs) help for fast cooling, but easily results in network congestion and introduces large cost. This paper proposed an efficient routing-based DTM scheme (ArR-DTM), which tries to balance the thermal distribution by providing complementary adaptive degree for lateral planes and finish thermal migration by regulating the adaptive degree in vertical direction. Experiments show that, under the same thermal limit, there is 13.1% to 23.8% performance improvement compared to the fully throttling based DTMs.
A Q band sub-harmonic mixer with wideband radio frequency (RF) and high intermediate frequency (IF) is proposed. The mixer employs a short-circuited band-pass filter (BPF) and a RF-IF diplexer, which provide proper terminations for the IF, RF, and local-oscillator (LO) signals simultaneously, and reject the major unwanted mixing products. A Q-band sub-harmonic mixer is designed and fabricated. The measured results show that the proposed sub-harmonic mixer can operate from 40 to 50 GHz for RF and support up to 10 GHz for IF bandwidth. As a down-conversion mixer, the measured conversion-loss is less than than 10.5 dB over the available RF band, while the minimum conversion-loss is about 6.8 dB at an RF of 45 GHz and IF of 5 GHz. As an up-conversion mixer, the measured conversion-loss is less than 11 dB over the available IF band, while the minimum conversion-loss is about 7.5 dB at an RF of 45.5 GHz and IF of 5.5 GHz.
A GaN HEMTs class EF3 power amplifier (PA) with π-type network for broadband operation is presented in this paper. The π-type network is constructed by shunt capacitance, series inductance and finite dc-feed inductance, where the series inductance includes the parasitic inductance effects of transistor. As a result, the topology can make full use of the parasitic effects of transistor to raise the operation frequency. Moreover, it is found that this topology can also increase the frequency bandwidth. For demonstration purpose, a PA prototype based on the topology is fabricated. Experimental results show that the amplifier can operate from 2.9 GHz to 4.0 GHz (fractional bandwidth 31.8%) with a measured drain efficiency higher than 67%, and the output power is greater than 37.4 dBm. The proposed structure can be a good candidate for design of high efficiency and broadband class E power amplifiers.
This paper presents a compact Ka-band TDD front-end chip with temperature compensation technology. The front-end chip is integrated with a passive switch, a low noise amplifier (LNA) and a power amplifier (PA). Temperature compensation bias network is used to reduce the gain ripple versus temperature, and co-design method between the amplifiers and the switch is used to enhance the bandwidth. The gain ripple is less than ±0.7 dB when the temperature ranges from −55°C to +85°C. The circuit works from 30.5 GHz∼39.1 GHz, with a 24.7% relative bandwidth. The chip is fabricated with GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The gain of the receiver (RX) link is 26.6 dB, and the noise figure of it is 2.95 dB at 36.5 GHz. The gain of the transmitter (TX) link is 26.0 dB, and the output 1 dB compression point of it is 16 dBm.