This letter presents the design and implementation of a LoRa-based wireless communication system aimed at monitoring of driver’s biomedical signals in the car environments. The proposed system is composed of a sensor node, a LoRa gateway, and a cloud server. Each sensor node includes four parts as microcontroller unit, data collection unit, wireless communication unit, and supplied power unit. The microcontroller unit is mainly designed as the signal processing module to deal with the detection of abnormal ECG symptom such as left bundle branch block (LBBB), which is the most common symptoms of myocardial infarction. The data collection unit contains a sequential stage of the instrumentation amplifier and the filter blocks. The notification of LBBB detection is then transmitted to the LoRa gateway by wireless communication unit. The LoRa gateway with multiple wireless interfaces is designed to collect the information from the sensor node to transmit to cloud server. The experimental results are conducted to evaluate the detection performance of LBBB by means of MIT-BIH arrhythmia database.
As the core part of underwater propeller, the performance of permanent magnet synchronous motor (PMSM) affects the thrust of it. In the operation of a PMSM, when the speed of PMSM is reversed, a position error of 180° will be generated by the traditional phase-locked loop (PLL). In this paper, an improved PLL based Luenberger observer is proposed to resolve this problem. The back electromotive force (EMF) was been obtained by the Luenberger observer. In contrast to the traditional PLL, the improved PLL has a different phase discriminator to tackle rotor position errors. Results of simulation and experiments show the effective convergence of the proposed improved PLL for rotor position errors and that the trust of propeller meets the requirements.
Three-dimensional stacking of ICs with through-silicon-vias (TSVs) is one of the most expected way to integrate an enormous scale system in a small footprint. Shortened distance and expanded interconnect area are proofed to enable low-power, ultra-wide bandwidth communication among logic, memory, and analog component. In the 3-D integrated system with massive vertical interconnects, noise coupling among TSVs can be problem, by degrading signal integrity. We made a simple model to estimate noise coupling among TSVs and analyzed the coupling strength against parasitic capacitance of liner oxide. A test chip is fabricated, and the noise coupling strength is evaluated through on-chip waveform capturing circuitry. The analytical result and measured result show good consistency, and they indicate smaller size TSVs show better noise isolation characteristics as well as process simplicity.
We developed a practical high-sensitivity 10-Gbit/s III-V compound-based avalanche photodiode (APD), and an receiver optical subassembly (ROSA) mounting the APD for 10-Gbit/s burst-mode operation. The 10-Gbit/s APD features an inverted p-down structure with a 200-nm InAlAs avalanche layer that produces low excess noise and a low dark current simultaneously at large gain. By combining our APD with a burst-mode trans-impedance amplifier (B-TIA), the resulting APD-ROSA exhibited -32.7 dBm for 10-Gbit/s burst-mode optical signals, which allows for a loss budget exceeding 35 dB on optical access networks such as passive-optical networks.
In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phase-clock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm2. An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.
In this paper, an efficient hardware architecture of scalar multiplication is proposed for elliptic curve cryptography. To reduce circuit area, we propose an elliptic curve operation unit architecture for Montgomery Ladder Algorithm in projective coordinates. The basic modular arithmetic circuit in elliptic curve group operation module is reused to realize coordinates transformation and y-coordinate recovery operation. Considering concurrent error-detecting and fault-tolerant, we improve the existing error detection scheme by reusing intermediate results and predicting fault. The simulation and DC synthesis results show that the scalar multiplication circuit designed according to the proposed architecture reduces the time cost of fault detection in single iteration to 1 clock cycle at 100% fault detection rate, and the efficiency is improved 96% than the existing literature.
A high-precision and low-temperature-coefficient bandgap voltage reference is proposed in 0.11 µm CMOS process. A temperature piecewise compensation circuit is added to a traditional bandgap reference to decrease the temperature coefficient (TC). The digital trimming technology has been used to solve the deviation of TC and output voltage resulting from process corner and mismatch. Simulation result shows that the bandgap reference achieves TC of 2.18 ppm/°C from -40°C to 125°C. Bandgap reference output voltage is 1.2 V with in the error of ±5 mV.
This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A high-linearity pseudo-differential push-pull input buffer with an anti-oscillation technique and a nonlinear parasitism eliminate technique is proposed to stably drive the pipelined stages while keeping low distortion. Moreover, a digital controlled aperture-error calibration is also employed with offset of comparators compensated in advance. Measurement results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 66.29dB and a spurious-free-dynamic-range (SFDR) of 85.62dBc at 80.1MHz input.
This paper presents a Ka-band 4-way combining power amplifier (PA) implemented in 65nm CMOS process. A T-type power combiner with loaded capacitors is proposed, which is cascaded with transformer-based power combiner to form a hybrid power combiner. The hybrid combiner can combine the output power of 4-way differential PAs into one channel compactly, and makes them achieve optimal load matching. The measured saturation output power (Psat), output 1dB compression point (OP1dB) and maximum power added efficiency (PAEmax) are 23dBm, 18.9dBm and 27% at 35GHz respectively. It achieves a 3dB bandwidth of 30.7GHz-38.5GHz within a core area of 0.26mm2.
We demonstrate a surface grating loaded VCSEL showing high power, good beam quality and stable single mode operation. In the structure, a single slow light mode propagating laterally along the long cavity of an oxide VCSEL can be selected thanks to the surface Bragg-grating. Experimental results of spectrum, L/I characteristics and beam quality with different device lengths are presented. A single mode power of over 80mW is realized with a narrow diffraction-limited divergence angle of 0.15° for a VCSEL with an oxide aperture of 4μm × 500μm under CW operation. A higher single mode power is expected through extending the device length with the proven scaling law.
An ultra-low power sub-bandgap voltage reference circuit fabricated in a standard 0.18-µm CMOS technology is proposed. Exploiting the negative temperature characteristics of VBE and VTH, a novel self-biased circuit configuration with a combination of a parasitic BJT and MOSFETs is employed to achieve a temperature-compensated sub-bandgap voltage reference with nanowatt power dispassion. The measurement results show that, the proposed circuit provides an average reference voltage of 261.6 mV with a variation coefficient of 0.86%. The line regulation (LR) is 0.26%/V in a supply voltage range of 0.9 V to 1.8 V at 27°C, and the power supply rejection ratio (PSRR) is -49 dB at 100 Hz. With one-time trimming, measurements performed over a set of 18 samples shows an average temperature coefficient of 25.9 ppm/°C in a temperature range from -20 to 100°C. The power dissipation is 1.8 nW with a supply voltage of 0.9 V at 27°C. The chip area is 0.0038 mm2.