The latch-up immunity of high voltage power clamps used in high voltage ESD protection devices is rapidly becoming very important in high-voltage applications. The conventional high-voltage ESD devices are unsuitable for new high-voltage applications due to their low holding voltage, low ESD robustness, and their large size. In this study, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified using a 0.35um BCD (Bipolar-CMOS-DMOS) process in order to achieve the desired holding voltage and an acceptable failure current. The experiment results show that the holding voltage of the stacking structure can exceed the operational voltage found in high-voltage applications. In addition, the stacking structure can provide a high ESD robustness.
Recognition of ionosphere phase contamination and multimode propagation is an important step in rejection of clutter spectrum spread for OTHR. Based on the algorithm of time reversibility, this paper proposes a method based on eigenvalue decomposition to detect multimode propagation. Besides, a cascaded technique composed of the two methods above is proposed to recognise contaminations. Another detection algorithm based on time series Hankel matrix is proposed, which will be suitable for more widely application. For the first time, the method based on backscatter sounding is also proposed for multimode recognition, and a hybrid method based on time reversibility and Hankel matrix is also proposed to distinguish phase contamination and multimode propagation.
In this paper, we propose a new channel selection method for IEEE 802.11 based wireless local area network (WLAN) using the 2.4GHz band. The proposed algorithm searches the nearby access points (APs) through channel scanning. The scanned APs are classified into shared APs using the target channel and interference APs using the channels adjacent to the target channel. The proposed method evaluates the achievable rate by separately considering the losses by shared APs and interference APs, and selects the channel with the maximum achievable rate. The performance of the proposed algorithm is compared to those of existing channel selection techniques through field tests in practical WLAN environments.
This paper investigates a network consisting of some CR terminals distributed between two primary transceivers. In the proposed network model, CR nodes assist the primary transmission as a two-way amplify-and-forward relaying scheme when the primary transceivers are in operation. By using distributed beamforming techniques among CR nodes, we propose an optimal solution to maximize the performance of spectrum sensing in terms of signal-to-noise ratio (SNR) at the CBS while satisfying the quality of service requirements of primary receivers. We demonstrate the superiority of sensing performance in the proposed method by relaxing the problem into the semidefinite form and we achieve the maximum value of SNR in the CBS by using an iterative algorithm.
A harmonic rejection mixer (HRM) with current mirror amplifier for digital TV tuner applications is proposed. In the proposed HRM, gain ratio can be set accurately using the current mirror amplifier to achieve high harmonic rejection ratio without mismatch calibration circuits. Owing to a folded switching stage, a harmonic rejection ratio of the HRM is also immune to a supply voltage variation and the HRM can be designed at a lower supply voltage compared to a conventional HRM. A third and fifth-order harmonic rejection ratio of the proposed HRM are 52.6 and 50.8dB. The harmonic rejection mixer consumes 11.5mA from 1.5V supply voltage.
A novel method of using bypass coupling SICC resonator to generate transmission zeros (TZs) in filter stopband to improve upper stopband attenuation is presented. A SIW quasi-elliptic function filter with bypass coupling SICC resonators is designed and fabricated to validate the method. The results show the method is effective to improve the filter stopband performance.
In this paper we present a high performance and low power media cache structure using a dynamic fetching mechanism. The proposed cache consists of three parts, i.e., a dual direct mapped cache, a fully associative spatial buffer, and a dynamic fetch unit. When a cache miss occurs, the dynamic fetch controller generates fetch signals for one of three block sizes (e.g., 64-byte, 128-byte, or 192-byte) depending on information that is kept on recent block access patterns. Simulation results show that the proposed cache can achieve better performance than a 2-way or 4-way set associative cache with twice as much space. Also, compared with a victim cache, the average memory access time is improved by about 15% on media applications. It is also shown that power consumption of the proposed cache is around 60% lower than other cache systems.
In this paper, a post-breakdown resistance value of antifuse cells has been calculated with respect to breakdown spots. Also, the effect of body doping concentration and source/drain abruptness on the post-breakdown resistance has been observed in the case of gate underlap and overlap structures. Based on simulation results, we have proposed some ways of making the post-breakdown resistance distribution uniform.
In this paper, a novel small dual band-notch ultra-wideband planar monopole antenna with switchable functions is presented. Impedance bandwidth of the proposed antenna is approximately 136% with VSWR<2 in the frequency range of 2.2GHz-11.6GHz. By inserting a U-shaped slot and SES structures on the patch of antenna, the dual band-notch characteristics are obtainable. The technique of on/off switching of notched bands is based on mounting three pairs of PIN diodes at a certain locations on antenna structure.
In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100µW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG.
Potential of hardware acceleration of the method of moments using a heterogeneous multi-core processor. The parallel efficiency is almost 100% and the computational time is about 100 times faster than that using a conventional CPU.
This paper proposes a pump wavelength assignment scheme for an optical packet switch with parametric wavelength converters (PWCs) to reduce the number of different colored light sources while a predefined packet loss rate is satisfied. PWCs are separated into two sets. First set, each PWC has a different pump wavelength from each other. Second set, all PWCs have the same pump wavelength placed at the center of the transmission wavelengths. Increasing the number of PWCs in the second set reduces the number of different colored light sources. However, the packet loss rate increases. Therefore, the number of PWCs in the first set is minimized.
In this paper, power efficiency optimization scheme of charge pump circuit in NAND FLASH memory was proposed. The proposed scheme was implemented in program/erase charge pump by pump stage number control method. The maximum power efficiency of this pump is about 30%, and the maximum point is around 70% point of highest voltage level. So in this paper, to operate program/erase pump in highest power efficiency area, the pump stage number control scheme is proposed and evaluated in 20nm 64Gb MLC NAND FLASH memory circuit. Simulation result shows overall improvement of power efficiency, and at the wafer test about 10mA peak current reduction and overall improvement of power dissipation are found.
In this paper, a modified semi-circle patch and a semi-circle stepped impedance resonator are cascaded to design a compact lowpass filter with sharp response and wide stopband. This filter has 3-dB cutoff frequency at 1.55GHZ. The transition band is only 0.29GHZ from 1.55 to 1.84GHZ with -3dB and -20dB respectively. Maximum insertion loss is 0.4dB in the passband and stop bandwidth with attenuation level better than -20dB extends from 1.84GHZ up to 12.5GHZ and up to 15GHZ is greater than -10dB, hence wide stopband is achieved. Simulation and measurement results are presented and good agreement between them is achieved. Results show that we have obtained a high Figure-of-Merit (FOM) of 30433.
A self-oscillating class-D audio amplifier employing a multiple-pole feedback filter is introduced intended for portable multimedia devices. As the oscillation is based on the Barkhausen's criterion, the signal-dependent oscillation frequency is of great concern. Employing higher-order filters contributes to the stable oscillation frequency depending on the input amplitude as well as improves PSRR and THD. The concept is revealed comparatively with other works, and a design implemented in a 0.35um CMOS process under 3.3V supply is proposed and verified.
A finite-element time-domain beam propagation method is described for the solution of electron waveguide discontinuities. Scattering properties in steady state are evaluated with Fourier transform of a pulsed wave in time domain. A perfectly-matched-layer boundary condition is implemented into the electron waveguide simulations. The approach is applied to an electron resonant cavity, and it is confirmed that when treating a slowly varying electron wave function, the converged solution can be obtained with moderate time step size.
This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this scheme, a pseudo-random pattern generator(PRPG) generates test vector for each slice in multiple scan chains. Using scan disabling technique, the generated test vector is shifted into the scan chains until it is compatible with its corresponding slice for a deterministic test set with don't care bits. An automatic test equipment (ATE) only needs to store the control signals instead of test data. The proposed scheme that is based on the standard scan and uses any test set with don't care bits is widely applicable and easy to deploy. Its hardware overhead that is a PRPG, phase shifter, MISR and scan disable signal is very low. Theoretical analysis and experimental results show the proposed scheme can achieve higher compression gain compared with previous low cost scheme when care bits are few.