In this letter, a low-power non-coherent BPSK demodulator which is applicable to implantable biomedical devices is described. The proposed demodulator adopts the dual band filtering for recovering the timing and data in non-coherent way. The circuit has been fabricated with a 0.18µm CMOS technology and the power consumption of the proposed demodulator is measured at 82µW with a 2MHz carrier frequency achieving 1Mbps data rate.
In automotive radar systems, only a small number of snapshots are available for direction-of-arrival (DOA) estimation in high mobility scenarios. We here propose a closed-form single-snapshot maximum likelihood (ML) DOA estimator based on the phase-comparison technique. The estimator can be effective in a wide field-of-view (FOV) scenario and is robust to gain-mismatch effects among antenna elements. Computer simulations are conducted to confirm the effectiveness of the proposed method.
This letter describes the design of a triple-band Global Positioning System (GPS) receiver that simultaneously covers the L1, L2 and L5 frequency bands. The proposed receiver uses an image-rejection technique that can separate signals from the three frequency bands to three corresponding ports. It uses a single RF path containing a low-noise amplifier (LNA), and active and passive mixers with a pair of local oscillator signals. The triple-band GPS RF front-end chip is fabricated using 130nm CMOS technology, and has a noise figure of less than 7.1dB and an S11 coefficient of less than -10dB in the frequency range 1.15-1.6GHz. The experimental results demonstrate a 35-40dB image rejection ratio at each output port with a power consumption of 7.2mW (LNA and mixers) using a 1.2V supply voltage.
In this letter, novel class-F and inverse class-F power amplifier (PA) topologies were proposed, simulated, realized and measured for 2.7-2.9GHz frequency band by using Gallium Nitride high electron mobility transistor (GaN HEMT). Realizations are made on Rogers TMM3 dielectric material which has 0.381mm thickness and 3.27 dielectric constant. Proposed class-F and inverse class-F PAs have 10W (40dBm) output power with 76% and 82% power added efficiency (PAE), respectively. Both PAs have state-of-the-art PAE performance compared to the PAs in the literature. Furthermore, the measurement results show that; under the same operation conditions, the inverse class-F PA has greater PAE than the class-F PA.
The continuously widening design productivity gap in the past few decades gives high incentives to counterfeiting ICs. Existing intellectual property (IP) protection schemes demand high overheads, and some techniques like watermarking do not facilitate tracing of illegal users. In this letter, we propose a novel fingerprinting method based on post-processing on circuit partitions. We evaluate our method on the ISPD98 benchmark suite. The experimental results demonstrate the effectiveness of the proposal. The fingerprinting design is distinct because the Hamming distance between fingerprinted IP designs is large enough to resist a collusion attack.
A high-speed data-search mechanism, called a synchronous overlapped search mechanism (SOSM) that enables a next-word search after searching just a few bits of the current word by simple pre-computation in most cases, is introduced for a content-addressable memory (CAM). Since there are no delay elements in the proposed hardware based on the SOSM, the hardware is robust against timing variation, maintaining high-throughput computing under serious process variation. A 128×64-bit CAM is designed with considering 30% variations of threshold voltages under a 45nm CMOS technology and operates at 4.2× faster throughput than that of a conventional CAM with 12.3% energy overhead.
A high-performance VLSI architecture for H.265/HEVC loop filter is proposed. The architecture is implemented by a parallel register array that consists of 8×8 registers with two data flow directions. The register array computes the sub-blocks of four different coding tree blocks at the same time based on the analysis of the computation order. This leads to the small number of registers used in the register array. The architecture computes 4K UHD at 30fps in real-time. The size of the synthesized design is 54K gates. The operating clock frequency is 225MHz in TSMC 65nm process. If the degree of parallelism is increased to four, the architecture can compute up to 8K UHD at 60fps.