This letter proposes two new realizations of current-mode (CM)quadrature oscillator (QO) using CDTA (Current Differencing Transconductance Amplifier) as the active element. The proposed circuits are canonic in component count and use two grounded capacitors which is ideal from IC fabrication point of view. Both the oscillator circuits provide current controllability of frequency of oscillation (FO) and the circuits enjoy the advantage of independent control of condition of oscillation (CO) and FO which makes them suitable as variable frequency oscillators (VFOs). B2SPICE simulation results are included that validate the working of the circuit.
This paper presents a virtual reconfigurable architecture (VRA)-based evolvable hardware for automatic synthesis of combinational logic circuits. The VRA processor is implemented on a Xilinx FPGA and works through two-stage evolutions: (1) finding a functional circuit, and (2) minimizing the number of gates used. To optimize the algorithm performance in the evolutionary process, a self-adaptive mutation rate control scheme is introduced. The efficiency of the proposed methodology is tested with the evolution of a 3-bit multiplier. The obtained results demonstrate that our approach improves the evolutionary design of electronic circuits in terms of quality of the evolved circuit as well as the computational effort.
Implementation of a correlation-based learning rule, Spike-Timing-Dependent-Plasticity (STDP), for asynchronous neuromorphic networks is demonstrated using `memristive' nanodevice. STDP is performed using locally available information at the specific moment of time, for which mapping to crossbar-based CMOS-Nano architectures, such as CMOS-MOLecular (CMOL), is done rather easily. The learning method is dynamic and online in which the synaptic weights are modified based on neural activity. The performance of the proposed method is analyzed for specifically shaped spikes and simulation results are provided for a synapse with STDP properties.
In many cases the average fingerprint ridge frequency in the whole fingerprint image should be determined. This parameter is, among other things, very important in procedures, where so-called fingerprint reference point has to be located. Unfortunately, as far, ridges frequency has been determined a priori, on the basis of anthropological measurements of the human population. This parameter is established as 10pixels, regardless of captured fingerprint image resolution. Until now it is assumed, that this resolution is equal to 500dpi. In practice, scanners obviously work with different resolution. This point of view has been revised and a new method of fingerprint ridge frequency measurement was introduced. This method allows to precisely calculate fingerprint ridges frequency - individually for any fingerprint image. The new approach allows determining more precisely, among other things, so-called fingerprint reference point, which is an important element of fingerprint recognition procedures.
In this paper, a new low-VDD CMOS bandgap reference circuit with small layout area and low power consumption is proposed. The proposed circuit delivering its output voltage below 1V has its Proportional-To-Absolute-Temperature (PTAT) term compensated by the Complementary-proportional-To-Absolute- Temperature (CTAT) voltage thereby suppressing a change in its output voltage regardless of temperature and VDD variations. Using a commercial CMOS 0.18-µ m process, the proposed circuit has been verified to be able to save its layout area by 48.7% and the power consumption by 29.9% compared with the previous sub-1-V-output bandgap circuit.
A 3D node localization scheme for WSNs is developed in this paper. In the scheme, a single mobile beacon submits UWB signals to the sensor nodes to help the whole network localize. Each sensor node receives the UWB signals and adopts TOA technique to measure the distances to the mobile beacon. SDI is proposed as the 3D positioning algorithm executed locally on each sensor node, and simulation is provided to compare it with two representative positioning algorithms, Min-max and Lateration, in terms of some evaluation parameters. The analysis in theory and the simulation show that our scheme can be a utilitarian 3D node localization scheme for WSNs.
In this paper, a multimode precoder design for space-time block code (STBC) is investigated, which varies the number of streams depending on the channel condition. We develop a design criterion of minimizing the vector symbol error rate and derive an efficient offline algorithm to generate precoders. Simulation results show that the multimode precoded STBC (MM-STBC) provides substantial performance improvements compared with the single mode precoded orthogonal STBC (SM-STBC) for a fixed data-rate. It also outperforms the multimode precoded multiple-input multiple-output (MM-MIMO) system when feedback rate is very limited.