This paper presented a simplified hardware architecture of the block cryptographic algorithm, HIGHT, for wireless applications like a RFID system. We have modified the original HIGHT algorithm that reduced the critical path in the key scheduler and dismissed redundant logics sharing encryption and decryption datapathes, and thereby yield a smaller silicon area. The proposed HIGHT supporting both encryption and decryption had 2,608 gates, 13% smaller than the original HIGHT design excluding decryption block. It consumes the average power 10.8µW at 2.5V for 100kHz. It can be applicable to passive RFID tag without serious difficulty in size and power. Also, the maximum clock frequency of 125MHz allows a data throughput rate of 235Mbps that can support cryptography of high-speed multimedia data.
This paper is concerned with real-time incremental face recognition for home service robots. For this purpose, we use an Incremental Tensor Subspace Analysis (ITSA) to enroll and recognize the user's face through low-price robot camera when robot performs the real-time customized service in home environments. Furthermore, we perform face recognition based on face database constructed in u-robot test bed environments in ETRI (Electronics and Telecommunications Research Institute). Thus it can be used as a core technique in conjunction with Human-Robot Interaction (HRI) that can naturally interact between human and robots in home robot applications. The experimental results on face database reveal that the presented method shows a good performance in comparison with the well-known methods in distant-varying environments.
A novel area-efficient on-chip feedback delay element (FDE) has been designed and evaluated in 0.18-µm CMOS technology. The circuit utilizes positive feedback to achieve both digitally controlled propagation delay and programmable duty cycle with only 9.5% silicon area of the conventional capacitor-loaded delay element (DE). The proposed FDE with monotonic delay step is suitable for use in area-sensitive and high-speed CMOS VLSI applications for memories and CPUs.
This paper describes a low-voltage design for a pipelined ADC that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output ranges of all MDACs by 50% compared to the ADC's input. We designed a 10-b pipelined ADC with the proposed front-end MDAC using a 90-nm CMOS process. The ADC achieved 2.0-Vpp rail-to-rail operation at only a 1-V supply and a 57.5-dB SNDR with only 3.4mW at 30MS/s despite using conventional folded-cascode op-amps.