This paper proposes a low power read-out integrated circuit (ROIC) for multiple sensors having a DC output signal. It comprises a chopper-stabilized instrumentation amplifier (CSIA) followed by a second-order incremental analog-to-digital converter (IADC). The CSIA has a dual-frequency path to effectively eliminate any 1/f noise and offset. A variable gain module (VGM) is also connected to the CSIA to improve its range of potential applications. A CMOS buffer amplifier followed by the CSIA is used to achieve the ROIC’s linearity and drive capability. The back-end of the ROIC has a switched-capacitor IADC to provide a digital output. The correlated double sampling (CDS) technique was used in the IADC’s first integrator to reduce the offset and noise. The combination of these techniques enables the ROIC to achieve an input referred offset of 5μV and a best error voltage of ±0.01mV. The ROIC was implemented in 0.18μm CMOS technology. It occupies an area of approximately 2.56mm2 and consumes 835μA of current from a 1.6V of supply voltage.
As the electrical characteristics of tunnel field-effect transistors (TFETs) are greatly influenced by the source junction and the gate spacer, the effects of these parameters are analyzed by technology computer-aided design simulation. As a result, it is found that an ON-state current of TFETs can be improved by +161.8% through the high-κ spacer of an appropriate length when the source junction does not overlap the edge of the spacer. In addition, it is confirmed that an intrinsic delay time which determines the high frequency characteristics is also reduced by -65.9% because an increase of entire gate capacitance, a side effect of the high-κ spacer, is negligible.
A highly efficient and broadband continuous Doherty power amplifier (DPA) using modified harmonic matching structure is proposed in this paper. The proposed structure can match the fundamental and harmonic impedance of the carrier power amplifier and peaking power amplifier (PA) precisely. To verify this structure, A highly efficient and broadband Doherty power amplifier based on this structure is designed and fabricated using a CGH40010F GaN HEMT packaged device. The measurement results illustrate that drain efficiency (DE) of 68.1%-72.1% at the saturated output power (Pout) and 48.4%-63.5% at 6 dB output back-off (OBO) is achieved across the band 1.6-2.1 GHz with the saturated output power is about 43.2-44.5 dBm.
In the physical design of VLSI circuits, the congestion generated in placement stage tends to enlarge the total wirelength (TWL) and further worsens the timing and routability. In this letter, a local congestion elimination technique is proposed which can be compatible with available commercial P&R EDA tools. Driven by overflow value, the optimal keepout margins being added around the highest pin cells in specific congestion regions are searched using simulated annealing (SA) algorithm and ant colony optimization (ACO) algorithm respectively to ameliorate local congestion. Experimental results have shown that the proposed technique can reduce the design rule violations (DRV), shorts and TWL significantly.
This paper presents a pure hardware implementation of CRYSTALS-KYBER algorithm on Xilinx FPGAs. CRYSTALS-KYBER is one of 26 candidate algorithms in Round 2 of NIST Post-Quantum Cryptography (PQC) standardization process. The proposed design focuses on maximizing resource utilization by reusing most of the functional modules in the encapsulation and decapsulation processes of the algorithm. For instance, the hash module integrates several different hash functions in one module. Efficient parallel and pipelined computations are applied in the NTT module. Through the analysis of simulation and synthesis results, it is found that the proposed work has the advantages of higher frequencies and lower execution times. The scheme operates at 155 MHz and 192 MHz frequencies on Xilinx Artix-7 and Virtex-7 FPGAs, respectively. Compared with the performance of an embedded Cortex-M4 processor, the hardware implementation can achieve a maximum speedup of 129 times for encryption/decryption.
Negative impedance convertor is introduced to build a high input impedance chopper IA for implantable EEG recording. The compensation theory is analyzed in detail to reveal the characteristics of the impedance boosting method. The proposed chopper IA achieves very high input impedance of 18.9 GΩ and 18.5 GΩ at DC and 100 Hz respectively. It can reach 5.8 GΩ even at 1 kHz. With the common-mode feedback loop, up to 600 mVpp common-mode interference tolerance and 97 dB CMRR are achieved. The amplifier is implemented in a 0.18µm standard CMOS process and takes a power consumption of 1.34 µW with a 1.2 V supply. The mid-band input referred noise PSD is 130 nV/sqrt(Hz) and an NEF of 4.89 is obtained.
Fractional orthogonal frequency division multiplexing (FrOFDM) exhibits considerable flexibility in the axis of multiplexing and a medium characteristic between OFDM and Nyquist optical time division multiplexing. FrOFDM subcarrier effect on nonlinear distortion in long haul transmission has not experimentally been verified. In this work, we used a highly nonlinear fiber under relatively short transmission conditions for experimental emulation of nonlinear signal distortion under long haul transmission conditions considering no phase modulation in time domain for non-telecom application. We examined the suppression effect on the distortion and confirmed that, FrOFDM subcarriers greatly suppress nonlinear distortion.
This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to reduce the static current, thereby obtaining ultra-low leakage power consumption. Post-layout simulation results demonstrate that the proposed LS implemented with SMIC 55-nm technology can convert 140mV low-voltage to 1.2V. Meanwhile, when evaluated with the low supply voltage of 0.3V at 1MHz frequency, the transition energy of the presented LS is 87.35fJ. Moreover, the static power consumption and propagation delay are only 64.2 pW and 18.07ns, respectively.
In this work, the thermal effect in the dynamic on-resistance (Ron) degradation of normally-off p-GaN AlGaN/GaN HEMTs on SiC substrates has been analyzed using pulse-mode voltage stress. Compare to the significant degradation characteristics of GaN-on-Si HEMTs, a suppressed dynamic Ron degradation is achieved in GaN-on-SiC due to higher thermal boundary conduction with less ionized acceptor-like buffer traps. Different electrical characteristics have been discussed to reveal the traps mechanisms related to thermal effect. Finally, two-dimension device simulation has been carried out to probe the physical insight into the thermal effect on the dynamic Ron degradation.
Dual-half bridge (DHB) converter is a novel family of phase-shifted full-bridge (PSFB) converter, and it can obtain a significant improvement in conversion efficiency compared to the traditional PSFB converter. However, the main drawback of DHB converter is that only the energy stored in leakage inductor can be used to discharge the junction capacitors of switches. All switches tend to lose zero-voltage switching (ZVS) under light load conditions, which will significantly degrade efficiency. This paper proposes a simple and effective method to extend the ZVS range of DHB converter. By making the DHB converter operating in discontinuous conduction mode (DCM) and widening the dead-time, the energy stored in the magnetizing inductors of transformers can be used to discharge the junction capacitors. Without additional auxiliary components, the ZVS operation under light load conditions can be obtained. Experimental results confirm the validity of proposed method.
A hybrid rectifier integrating the parallel-type synchronized switching harvesting on inductor (PSSHI) and synchronous electric charge extraction (SECE) is proposed. The hybrid rectifier can self-adjust its operations between Flipping/SECE and PSSHI/SECE according to the input PE voltage. Furthermore, a simple circuit implementation with the capability of cold-start and self-power is presented. The prototyped rectifier can extract the peak power of 85.7µW with the PE open-circuit voltage of 3V and the rectified voltage of 4.14V. Its performance is at least twice that of the full-wave bridge rectifier in terms of peak output power and operating voltage range. It can cold-start successfully from a lower PE voltage and charge the load to a higher voltage.