An injection-locked fractional frequency multiplier (ILFFM) based on a ring VCO is proposed. The ILFFM can output signals whose output-frequency step equal quarter of an input reference frequency (1/4×fref), with low-phase-noise characteristics due to injection locking. To realize this fractional frequency multiplication, an injection pulse selection circuit is demonstrated, which can select the appropriate injection pulse trains as to the VCO output phases. The proposed circuit was fabricated in 65nm CMOS process. When a 528-MHz (fref) reference signal was input, output frequencies of 4.5×, 4.75×, and 5×fref were obtained with low phase noise. A 1-MHz-offset phase noise with injection was -113dBc/Hz at the output frequency of 2.51GHz (=4.75×fref).
A novel approach for designing a quad-band bandstop filter is proposed by using dual-plane E-shaped defected structures and open-loop resonators coupled to the microstrip line. Through this design, the proposed filter features four conveniently adjusted stopbands, compact size and simple design procedure. The equivalent circuit model of the quad-band bandstop filter is derived before the design procedure is summarized. To facilitate the filter design, an approximate design rule for the resonant frequency of the E-shaped defected structure and the open-loop resonator is presented. As an illustrated example, a quad-band bandstop filter is designed and fabricated. The fabricated filter has four stopbands with center frequency at 2.37/3.52/5.20/5.76GHz and the rejection levels of the stopbands are all better than 31dB, verifying our proposed design concept.
In this paper, we discuss the implementation of the BCH decoder Chien search algorithm on a SIMD style programmable baseband processor with minimum memory footprint and processing time degradation. Due to the emergence of long BCH codes, the computational efficiency of the Chien search algorithm becomes a major implementation issue for BCH decoders. We minimize the memory usage and processing time of the BCH decoders by deriving a computation rule, which is used to efficiently generate the power terms of primitive elements upon the SIMD datapath, instead of storing all pre-computed terms in the memory.
An optimal polarization beam pattern synthesis method based on particle swarm optimization is proposed in this paper. It is flexible to synthesize any state of polarization and arbitrary shape of power pattern. There is no limitation on the array geometry and element, and the proposed method is applicable for different array synthesis problems. Two typical examples, elliptical polarization synthesis with narrow main beam and linear polarization synthesis with shape main beam, are presented to show the potentiality of the proposed method.
An embedded Non-Volatile Resistive Memory IP with low power and high reliability is presented for application in RFID tags. The logic-based CuxSiyO resistive RAM employs a 2-transistor-2-resistor (2T2R) cell structure to reduce process variation and expand sensing margin. The feedback mechanism is adopted in the write process to prevent power consumption. A 64Kb RRAM IP is embedded in RFID tag test chip in 0.13µm logic process. Test results indicate that 6X margin is attained in resistance distribution at worst case and 22.2µW program power is achieved, which demonstrates the low power and variation-tolerant robustness.
A novel Doppler beam sharpening (DBS) algorithm based on chirp z-transform (CZT) is proposed in this letter to correct range cell migration (RCM) without prior knowledge of Doppler centroid. Iterations of conventional Doppler centroid estimation algorithms are avoided, and the impact of Doppler centroid estimation error is further circumvented. The processing steps combining DBS and CZT are given based on FFT, which are suitable for real-time projects. Simulation results prove the effectiveness of the proposed algorithm.
This paper presents the design and demonstration of an optimized quad flat pack (QFP) structure for radio frequency (RF) multi-chip module (MCM) application. In order to reduce large impedance discontinuities in the low-cost QFP, a new design scheme with cascade coplanar transmission line structure built into the lead frame has been developed. The optimized structure is accurately modeled in 3D model by utilizing ANSYS HFSS. S-parameter is utilized to help in understanding the contributing to the optimized QFP structure. The analysis results indicate that the optimized QFP structure can be fully capable of supporting 5.8GHz RF MCM application.
For the practical realization of precise processes or devices utilizing scanning nanoprobes, not only improvement in the wear resistance of the probe tip but also a stable electric contact at the sliding probe electrode is required. To meet both these requirements, the authors developed an anti-wear probe having a supporting Si tip and a metal electrode, both of which slide on the substrate simultaneously. Probes with various electrode materials were evaluated to investigate the key factors of the material choice for maintaining good electric contact over a long sliding distance. The results show that the optimal management of material hardness, surface roughness, and probe contact force was important to realize an optimum performance from the probe.
The TuMR reader was designed with high sensitivity for high areal density magnetic recording in the hard disk drive. The assembly process requires the use of solder jet welding on small connectors in the head circuit. The solder bridging problem is the cause of the major mechanical yield loss. This work considers how to resolve the bridging problem without degrading the TuMR sensor by examining the use of Nd:YAG laser reheating. The use of double laser pulses yields better results than the use of single pulses. The critical parameters of the TuMR sensor are monitored with the Quasi tester.
The multiple-reference-frame motion estimation (ME) is one of the features to improve the compression efficiency. However, the computational complexity for prediction increases in proportion to the number of reference frames. This paper proposes the reference frame selection algorithm for a hardware-based HEVC encoder. The integer-ME explores multiple reference frames to find the best one and the fractional ME is then performed for the best reference frame which is determined by the IME. Simulation results show that a significant time saving of 74% is achieved with a negligible drop in compression efficiency.
When multiple RFID tags have to be identified in an RFID system an anti-collision protocol must be used to avoid two tags responding at the same time. Tags must respond in different time slots in order to be identified, since current RFID systems do not allow readers to communicate with different tags simultaneously. Multiple Input Multiple Output techniques can be used along with Blind Signal Separation algorithms to identify multiple RFID tags at the same time, thus increasing the read-rate and reducing the time needed to identify large amounts of tags.
SATA has been widely used as the dominant hard disk storage technology. We tried to optimize the performance of SATA disks by devising a new cache algorithm that is aware of disk access time. To validate and test it, we implemented a simple but practical hard disk simulator. Real trace-driven simulations show that the proposed cache algorithm achieves up to 35 percent of improvement compared to LRU.