IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 11
Showing 1-12 articles out of 12 articles from the selected issue
LETTER
  • Wei Li, Houxiang Zhang, Hans Petter Hildre, Jun Wang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140168
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    Faced with the high computational complexity of UAV SAR raw signal simulators, a multi-FPGA system is developed. The system is based on a time-domain raw signal algorithm which can compute in real time and can be used for closed-loop simulation. In order to improve the efficiency of the SAR slant range computing, a modified non-restoring squire root algorithm for FPGA is designed. An improved method is presented to perform coherent accumulation of raw signal to decrease memory cost. The pipelined FFT and IFFT are used to compute the convolution in order to reduce delay. The SAR raw signal generation system is implemented and verified with real-time performance. It can simulate an imaging scene size of 640 * 640 point scatters with a PRF higher than 40 kHz.
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  • To-Po Wang, Shih-Yu Wang
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 11 Pages 20140250
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 23, 2014
    JOURNALS FREE ACCESS
    A low-power low-phase-noise K-band CMOS VCO with dual negative conductance (−Gm) structure for class-AB operation is proposed in this paper. By utilizing the dual −Gm structure, the negative conductance of the K-band VCO is effectively enhanced. Therefore, the severe startup condition for the K-band CMOS VCO can be alleviated, leading to reduced dc power consumption. Moreover, VCO cores operating in class-AB region exhibit enlarged voltage swings, resulting in an improved VCO phase noise. Based on the proposed architecture, the fabricated 0.18-µm CMOS VCO cores consume total 5.4-mW low dc power at 1.2-V supply voltage. At this bias condition, the measured phase noise is −106.15 dBc/Hz at 1-MHz offset from a 22.1-GHz carrier, the tuning range is 9.8%, and the output power is −7.1 dBm. Compared to the recently published K-band 0.18-µm CMOS VCOs, this work achieves low dc power consumption, low phase noise, and superior figure-of-merit (FOM).
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  • Hiroki Funato, Takashi Suga, Michihiko Suhara
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 11 Pages 20140272
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    An approach based on the analytical expressions of the fringe capacitance for describing the spatial resolution for Position Signal Difference (PSD) electric near-field measurements is addressed in this paper. The calculated full width at half maximum (FWHM) of the measured results by using PSD for the scanning over microstrip line using the proposed model were in good agreement with the measurement results. Furthermore, a new measurement technique for obtaining more accurate results of a normal component of electric near-field by eliminating the fringe capacitance is proposed. The demonstrated results when using the proposed method showed a better correlation to the simulated normal component of electric field than using conventional PSD. Finally, the role of probe displacement for Double Position Signal Difference (DPSD) measurements is also clarified by verifying the measurements using the electromagnetic simulated results.
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  • Wataru Yoshimura, Kenichi Ohhata
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140313
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 14, 2014
    JOURNALS FREE ACCESS
    A Resistor ladder is an important circuit block for parallel architecture analog-to-digital converters (ADCs). The output of ADC suffers from distortion due to kickback noise from comparators when the bias current of the resistor ladder is reduced to reduce its power dissipation. A technique of distortion compensation that cancels kickback noise by injecting compensation current to the resistor ladder has been known to overcome this problem. This technique, however, did not consider that kickback noise depends on the sampling frequency and variability of resistors. Therefore, we propose an automatic circuit for distortion compensation that detects the amount of kickback noise and properly adjusts the compensation current. The simulation results demonstrated that distortion could be reduced with the proposed technique even when the changes in sampling frequency and deviations in the resistor occurred.
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  • Hyejeong Hong, Jaeil Lim, Sungho Kang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140324
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 14, 2014
    JOURNALS FREE ACCESS
    Task scheduling for multicore processors typically has aimed at higher throughput and lower power consumption, but the lifetime reliability may be harmed if negative bias temperature instability is not considered together. In this letter, a task scheduling which extends lifetime is proposed. Cores are given the chance to recover as long as performance is not degraded. The degradation simulator shows that the proposed scheduling improves the lifetime of a multicore processor by up to 36% over the existing task scheduling.
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  • Yanwei Xiong, Jianhua Zhang, Ping Zhang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 11 Pages 20140330
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 23, 2014
    JOURNALS FREE ACCESS
    The analog to information converter (AIC) based on compressed sensing (CS) is designed to sample the analog signals at a sub-Nyquist sampling rate. In this paper, we propose a novel parallel multi-rate compressed sampling (PMCS) system. It has several parallel paths and each path has several low-speed analog-to-digital converters (ADCs). This system has simple structure and low sampling rate, which makes it easy to be implemented on hardware. Simulation results show that signals can be reconstructed in high probability even though the sampling rate is much lower than the Nyquist sampling rate.
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  • To-Po Wang, Chih-Yu Wu
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 11 Pages 20140342
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    A millimeter-wave 0.18-µm CMOS VCO with measured oscillation frequency from 82.25 to 87.43 GHz is presented in this paper. In this work, three varactor rows are utilized to improve the VCO tuning range. The first varactor row is deposited at bottom of the cross-coupled pair for alleviating the loading effect on the VCO core. Moreover, the other two varator rows are connected between the drain and source terminations of the cross-coupled pair for enhancing the tuning range. Compared to conventional differential Colpitts VCO, the loading effects on VCO core can be effectively alleviated. In addition, due to the second-harmonic superposition technique, the signal strength of the output signal (2fo) can be enhanced. The enhanced 2fo output signal is extracted from the middle of the varactors, resulting in an elimination of the required λ/4 micropstrip or coplanar waveguide (CPW) line for a RF choke. This leads to a minimized chip size of 0.549 mm2. Based on the proposed VCO architecture, the fabricated 0.18-µm CMOS VCO core consumes 5.8-mW low dc power at 1.0-V supply voltage. At this bias condition, the measured phase noise is −77.92 dBc/Hz at 1-MHz offset from an 84.02-GHz carrier, and the tuning range is 6.11%. Notably, this modified differential Colpitts VCO demonstrates the highest operation frequencies (82.25 GHz to 87.43 GHz) among previously published 0.18-µm CMOS VCOs.
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  • Dong-Ho Choi, Changsik Yoo
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140351
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    A clock and data recovery (CDR) circuit for 1.5–5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10−12.
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  • Dengyun Lei, Weijun Lu, Dunshan Yu
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140358
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 14, 2014
    JOURNALS FREE ACCESS
    In this paper, a resource-efficient acquisition method is proposed for binary-offset-carrier (BOC) modulated signal. Specifically, we divide the acquisition process into two steps to remove redundancy. By adopting time division multiplexing technology, the utilization rate of hardware is effectively improved. Furthermore, a general acquisition architecture with proposed method was implemented. Experimental results showed that the number of adders was reduced by 76.9 percent compared with previous methods.
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  • Jizeng Wei, Xulong Liu, Hao Liu, Wei Guo
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 11 Pages 20140361
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    In this paper, we incorporate the co-Z arithmetic with Protected NAF to build a dual-field scalar multiplication method in ECC (elliptic curve cryptography) with lower time complexity and higher security, called co-Z Protected NAF. The Protected NAF is the alteration of the original NFA against SPA (simple power analysis) attack. But the employed dummy operations, double-and-add-always, often results in two severe problems: the high time complexity and the vulnerability of safe-error attack. So, the speed advantage of co-Z point addition is leveraged to greatly compensate the time penalty incurred by Protected NAF. Meanwhile, not only does the co-Z not change the SPA immunity existed in Protected NAF, but the property of updating point P in it improves the security to resist the safe-error attack. Experiment results show that the co-Z Protected NAF can obtain 1.36 times speedup with respect to Protected NAF over GF(p), and is even faster than original NAF. And it can also counteract 30.7% time loss over GF(2m) caused by dummy operations. Furthermore, because the co-Z Protected NAF is only the optimization on scalar multiplication, only less than 1% extra area cost is generated to achieve its improvements in time complexity and security.
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  • Young-Jin Kim
    Type: LETTER
    Subject area: Storage technology
    2014 Volume 11 Issue 11 Pages 20140363
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 14, 2014
    JOURNALS FREE ACCESS
    In SATA hard disks, native command queuing (NCQ) and a cache can play important roles in boosting the performance. However, research on cache algorithms which can exploit the benefits fully from NCQ has been seldom reported till now. In this paper, we propose a novel cache algorithm which combines disk access time and access frequency in a more NCQ-friendly way to enhance the I/O performance. Real trace-driven simulations show that the proposed algorithm improves the overall I/O performance by up to 39.2 and 19.1 percent over LRU and a prior access time-aware cache algorithm, respectively.
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  • Zhen Xie, Yang Zhang, Longxing Shi
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 11 Pages 20140386
    Published: 2014
    Released: June 10, 2014
    [Advance publication] Released: May 19, 2014
    JOURNALS FREE ACCESS
    A method for estimating the 3D rendering performance of the SoC (System on Chip) in the early design stage is proposed. Commonly the rendering performance is evaluated by some widely used graphics benchmarks. However these benchmarks need the support of the OS (Operation System), which makes them impractical in the early design stage of the SoC. In this work, through building a linear regression model, low-level graphics performances are used to estimate the rendering performance of the system for specific graphics benchmarks. The benefit is that the low-level performances can be obtained in the early design stage by simulation, and the estimation can be made as well to help designers make decisions. Experiments show that the results estimated properly match with the practical performances measured.
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