IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 9 , Issue 19
Showing 1-8 articles out of 8 articles from the selected issue
  • Yves Bouvier, Kimikazu Sano, Munehiko Nagatani, Koichi Murata, Kenji K ...
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1504-1509
    Published: October 01, 2012
    Released: October 01, 2012
    JOURNALS FREE ACCESS
    A full-rate architecture 27-1 PRBS generator has been designed and fabricated in the in-house 0.5µm-emitter-width InP-HBT technology. This generator has wide-operating range from 0.1 to 48Gbps with an output swing of 345mVpp. Its power consumption is lower than 900mW. The circuit achieves error-free operation up to 12.5Gbps and we obtain correct signal sequence and good eye opening up to 48Gbps. Its FOM is lower than 2.57mW·GHz-1.
    Download PDF (1359K)
  • Bixia Zhang, Huaxi Gu, Yintang Yang, Kun Wang, Zhengyu Wang
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1510-1515
    Published: October 02, 2012
    Released: October 02, 2012
    JOURNALS FREE ACCESS
    Three-dimensional network-on-chip (3D NoC), which combines NoC with 3D IC technology, offers several prominent advantages, including reduced overall interconnection length and design flexibility. However, it suffers from the high chip temperature problem. In the ciliated 3D Mesh architecture, the competition for the port of the router is fierce. A new temperature and network competition-aware mapping algorithm is proposed to reduce the peak temperature and decrease the network competition. The new algorithm can realize the multi-objective mapping and ensure a lower time complexity. Simulation results show that our method achieves an appropriate balance between peak temperature and network competition.
    Download PDF (355K)
  • Hanjung Song
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1516-1521
    Published: October 02, 2012
    Released: October 02, 2012
    JOURNALS FREE ACCESS
    A novel dual feedback looped chaotic integrated circuit driven by a three-phase non-overlapping clock is presented. The proposed circuit consists of four MOS switches for S/H (sample and hold), a level shifter and two nonlinear functions for nonlinearity in the feedback. After optimizing of nonlinear functions for chaotic signal generation, the proposed circuit was simulated with SPICE program using a 0.6µm CMOS process parameter. For various control voltages, its chaotic dynamics such as time waveform, frequency spectra and bifurcation diagram were analyzed. We confirmed that the circuit can generate discrete chaotic signals in specific control voltages.
    Download PDF (1070K)
  • Julio Cesar Rosas-Caro, Pedro Martin Garcia-Vite, José Merced L ...
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1522-1527
    Published: October 03, 2012
    Released: October 03, 2012
    JOURNALS FREE ACCESS
    Several DC-DC converters based on voltage multipliers have been recently published with advantages such as high voltage gain and few inductors used. This paper presents a generalized topology from which several of the state of the art and new topologies may be derived.
    Download PDF (444K)
  • Yoseop Lim, Jaeseok Park, Sungho Kang
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1528-1533
    Published: October 03, 2012
    Released: October 03, 2012
    JOURNALS FREE ACCESS
    The demand for fault diagnosis has increased with the increasing complexity of VLSI devices. Defects that result from process variations may cluster in certain areas. When a large number of defects cluster in an area, diagnosing these defects is a challenging problem because defects frequently exist that are partially or completely dominated by other adjacent defects. The most common approach for modeling delay defects is the transition fault model. We propose a diagnostic method that can handle clusters of transition faults. The experimental results for the full-scan version of the ISCAS’89 benchmark circuits demonstrate the accuracy of the proposed method.
    Download PDF (163K)
  • Cesar A. Azurdia-Meza, Kyujin Lee, Kyesan Lee
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1534-1541
    Published: October 05, 2012
    Released: October 05, 2012
    JOURNALS FREE ACCESS
    Peak-to-average power ratio (PAPR) plays an important role in the design of wireless communication systems because a high PAPR decreases the efficiency of the power amplifier. A new family of Nyquist pulses was derived by applying a linear combination between two Nyquist pulses. The proposed Nyquist pulses are utilized for pulse shaping to reduce PAPR. The investigated pulses are characterized by a new design parameter (p), giving an additional degree of freedom to minimize PAPR for a given roll-off factor α. While keeping the same bandwidth, the frequency responses of the proposed filters are unique with different values of the parameter p. Simulations showed that the optimum proposed pulse shaping filters provide better performance in PAPR reduction compared to those of the RC filter and other existing filters evaluated in various systems.
    Download PDF (1414K)
  • Ze-zong Chen, Lin-gang Fan, Chen Zhao, Yan Jin
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1542-1549
    Published: October 09, 2012
    Released: October 09, 2012
    JOURNALS FREE ACCESS
    An S-band Doppler radar, named MORSE (Microwave Ocean Remote SEnsor), has been developed by Wuhan University to measure ocean wave spectrum. Six narrow beam antennas are equipped to obtain directional wave height spectrum. Each of the antennas has a 3dB bandwidth of 30 deg, and they are operated in time multiplex mode. The system was applied for a seven-day experiment on the coast of the East China Sea at the end of 2011. Directional wave height spectra are obtained and presented. The time-series of non-directional wave spectrum and significant wave height fluctuate in the frequency of semidiurnal tide. This signature, consistent with ocean wave properties, suggests that MORSE has been able to measure the directional wave height spectrum.
    Download PDF (471K)
  • Morteza Nabavi, Maitham Shams
    Type: LETTER
    2012 Volume 9 Issue 19 Pages 1550-1555
    Published: October 11, 2012
    Released: October 11, 2012
    JOURNALS FREE ACCESS
    Parallel Transistor Stacks (PTS) has been shown to be an effective technique for improving the speed of digital circuits operating in the subthreshold region which comes at the cost of power consumption and area. However, our experience shows that using PTS is not beneficial in all cases. In this paper, we present a methodology to identify whether using PTS is beneficial (or not) in a particular CMOS technology and what transistor sizing can be employed to maximize the circuit speed. Our technique is based on analyzing the Current-Over-Capacitance (COC) ratio of PMOS and NMOS transistors. The results of incorporating the proposed methodology in a 4-bit comparator and a 19-stage inverter ring oscillator, using 90nm CMOS technology, illustrate 26% and 40% extra improvement compared to the blind use of PTS, respectively.
    Download PDF (333K)
feedback
Top