IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10, Issue 8
Displaying 1-10 of 10 articles from this issue
REVIEW PAPER
  • Yasuo Ohtera, Hirohito Yamada
    Article type: REVIEW PAPER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2013 Volume 10 Issue 8 Pages 20132001
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    This paper reviews the application of photonic crystals (PhCs) and related periodic structures to spectrometers and wavelength filters. In the first half of the paper in-plane type spectrometers utilizing superprism effect are reviewed. In the latter half out-of-plane and surface-normal type devices, where guided mode resonance (GMR) plays a center role, are described. Finally, Bragg reflection type wavelength filters are dealt with.
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LETTER
  • Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi ...
    Article type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 8 Pages 20120795
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    Quadratic permutation polynomial (QPP) interleaver is more suitable for parallel turbo decoding due to it is contention-free. However, the parallel address generation of QPP is area-consuming when the parallel degree P is large, and the data shuffle between memory banks and processing elements (PE) introduces large interconnect cost. This paper first evaluates the area and power cost of three typical Parallel Address Generators (PAG) and four typical Data Shuffle Networks (DSN) from academic and industrial area, and then proposes a novel general QPP interleaver with a highly area-efficient PAG and an associated DSN. Our QPP interleaver can support general parallel turbo decoder design. Experimental results show that, for P=64, the area and power cost of the PAG are on average 9.2% and 9.8% of that of the evaluated respectively. Meanwhile, the DSN can also achieve a slight hardware cost reduction, compared with the evaluated works.
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  • Huanyao Dai, Yongzhen Li, Jianling Cui, Huidong Qiao
    Article type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 8 Pages 20130054
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    Blanketing jamming is widely used in electronic jamming war, whereas the existing electronic countermeasures maybe invalided in the future. By using the spatial polarization characteristic (SPC) modulation effect on jamming signal as antenna scanning, a novel side-lobe blanketing jamming suppression method is proposed. It processed the sample data by using pre-knowledge of jamming direction, SPC, then the orthogonal polarized component and polarization states of receiving signal can be estimated. The polarization filtering is designed to achieve the objective of suppressing jamming. The novel method enables single polarized radar own anti-jamming ability in polarization domain, where the suppression performance can reach to 20dB. The validity has been proved by simulation experiment.
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  • Jian Wang, Yi Su
    Article type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 8 Pages 20130125
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    Bow-tie antenna is widely used for pulse radiation, but the radiation efficiency is less than 30%. In this letter, a novel method is presented to improve the efficiency by exploiting the energy in end reflections, which are thought to be harmful and usually suppressed in the reported literatures. When the exciting pulse is bipolar and monocycle, it is indicated that, the end reflection can be used for producing a pulse with increased peak value by optimizing the antenna length. The simulation results show that the pulse radiation efficiency can be increased 100% with the presented method.
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  • Geun Rae Cho, Kyung Woon Hwang, Tag Gon Kim
    Article type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 8 Pages 20130142
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    A bandgap reference circuit that uses high-voltage drain-extended MOS (DeMOS) devices is presented for high supply voltage application without using a voltage regulator for the bandgap core circuit. The bandgap reference circuit was fabricated using commercially available 0.18µm high-voltage DeMOS technology. Measurement result of the chip shows that the reference voltage change rate for VDD variation from 5V to 30V and for the temperature variation from -40°C to +140°C were 1.16mV/V and 0.84mV/°C, respectively. The measured reference voltage with the supply voltage of 15V at room temperature was 2.487V. The current consumption and the active area were 3.2µA and 320×345µm2, respectively.
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  • Yanhan Zeng, Yunling Luo, Jun Zhang, Zhuqian Gong, Hong-Zhou Tan
    Article type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 8 Pages 20130154
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    A voltage reference of low supply voltage and low power consumption has been proposed and simulated using 0.18µm process in this paper. Utilizing the body effect, temperature compensation is achieved without using any other special devices such as thick gate oxides MOSFETs with higher threshold. The simulation results show that the line sensitive is 0.73ppm/V in a supply voltage range of 0.6V to 2V and the temperature coefficient is typically 23.7ppm/°C in a temperature range of −20°C to 80°C with the power consumption of 30.5nW at room temperature. The power supply rejection ratio is −40dB at 10Hz and −32dB at 100Hz, respectively.
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  • Christophe Van Praet, Guy Torfs, Johan Bauwelinck, Jan Vandewege
    Article type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 8 Pages 20130156
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    A novel large input range source-follower based bi-quad filter cell is proposed offering an additional degree of freedom to the position of the poles and zeros. Simulation results of a 4th order fully differential elliptical filter in a 0.13µm CMOS technology confirm a power consumption of 160µA @ 1.2V, an IIP3 of 6.3dBm and a steepness of 177db/decade.
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  • Youngcheol Park, Jongkyun Kim
    Article type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 8 Pages 20130171
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    In this study, multi-harmonic voltage reflections are analyzed for compact power amplifiers that can be integrated into micro-sized radio units. By combining impedances at DC and harmonic frequencies throughout the transmission lines of power amplifier circuits, this method is used to reduce analytically the footprint of these circuits. Further, a cost function that takes the occupied area and the circuit performance into account is used to measure the effectiveness of the suggested method. For the sake of verification, a 10W class-J power amplifier is designed for 2.0-2.5GHz, and showed a 35% reduction in its footprint, a peak efficiency of 71.3%, an output power of 40dBm.
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  • Yuki Yamashita, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, ...
    Article type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 8 Pages 20130174
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    This paper describes the design of 5-GHz fully integrated self-biasing power amplifier (PA) for wireless transmitter applications in a 0.18-µm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3mm2. The measurement results indicate that the PA delivers 16.4dBm output power and 35.4% power-added efficiency with 2.3V power supply voltage into a 50Ω load.
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  • Makoto Mita, Manabu Ataka, Hiroshi Toshiyoshi
    Article type: LETTER
    Subject area: Micro- or nano-electromechanical systems
    2013 Volume 10 Issue 8 Pages 20130187
    Published: April 25, 2013
    Released on J-STAGE: April 25, 2013
    JOURNAL FREE ACCESS
    We have developed a new microelectromechanical logic device using the MEMS (Micro Electro Mechanical Systems) technology. This device consists simply of a single cantilever and two driving electrodes with two contact pads for electrostatic operation. Both exclusive NOR (XNOR) and exclusive OR (XOR) logic devices have been realized using this simple construction.
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