A 33 Gbit/s equalizer chip fabricated in 0.13 µm BiCMOS technology is presented. The proposed equalizer prototype includes adaptive continue time linear equalizer (CTLE) with middle frequency compensation and adaptive half-rate look ahead decision feedback equalizer (DFE). The slope detection based CTLE employs a two-path amplifier to adjust the ratio of the high frequency and low frequency adaptively, and a middle frequency amplifier dedicated to provide an appropriate compensation in the intermediate frequency range. For the half-rate DFE, by using a look ahead structure and an analog LMS algorithm circuit, the performance is improved in speed and area. Measurement results show that the equalizer chip can compensate lossy channel with a loss of 26 dB at 20 GHz effectively and the data rate can be up to 33 Gb/s under 3.3 V power supply, the total power consumption is about 726 mW at 33 Gb/s data rate.
Video sensor data has been widely used in automatic surveillance applications. In this study, we present a method that automatically detects the foreground by using depth information. For real-time implementation, we propose a means of reducing the execution time by applying parallel processing techniques. In general, most parallel processing techniques have been used to parallelize each specific task efficiently. In this study, we consider a practical method to parallelize an entire system consisting of several tasks (i.e., low-level and intermediate-level computer vision tasks with different computational characteristics) by balancing the total workload between CPU and GPU. Experimental results with a pig monitoring application reveal that the proposed method can automatically detect the foreground using CPU-GPU heterogeneous computing platforms in real time, regardless of the relative performance between the CPU and GPU.
A low power micromechanical capacitive accelerometer system is presented with hybrid signal output in this paper. Correlated-double-sample (CDS) technique is utilized in the front end circuit to ensure low noise output signal. The accelerometer system provides direct digital output, and analog output is also available. The chip is implemented in a standard 0.35 µm CMOS process with a power dissipation of 19 mW from a single 5 V supply. The digital output signal achieved a noise floor of 2 µg/√Hz, and the precision of analog output signal is 3.75 µg/√Hz.
This paper describes a CMOS fully-differential switched-capacitor (SC) single-loop Sigma-Delta (ΣΔ) modulator specialized for highly precise micromechanical capacitive sensors. This design adopts a single-loop, fourth-order, one-bit quantization architecture with feedforward paths for lower nonlinearities and power consumption. Systematic optimization is used to avoid deterioration in conversion accuracy caused by capacitor mismatch. Chopper-stabilization and double-sampling techniques are also employed to enhance performances in noise depression. Manufactured in a standard 0.35 µm CMOS process, the ASIC occupies an area of 5.32 mm2 including 25 pads. This modulator achieves a signal-to-noise ratio (SNR) of 105.2 dB and dynamic range (DR) of 113.7 dB. The whole chip consumes 12.6 mW from a 5 V supply.
The design and implementation of a digital controller for a boost power factor correction (PFC) converter under continuous current mode is presented to reduce the harmonic distortion. Based on the circuit structure of boost PFC converter, the total digital control loop is simply implemented to improve the power factor of converter and reduce the calculation burden of digital controller. Meanwhile, the optimized digital pulse width modulator (DPWM) is adopted to improve the regulation performance of digital controller. The boost PFC converter with the proposed digital controller has been implemented via the FPGA platform, and experimental results indicate that the digital PFC converter with the proposed digital controller can aim high regulation linearity, power factor and output stability.
A modified version of the flipped voltage follower (FVF) with class AB operation and very low output resistance is presented. Instead of passing one of the large bidirectional output currents through the voltage following transistor, which considerably degrades the output resistance as in other variations, the proposed circuit maintains a constant current in this device and, hence, a very low output resistance. Complementary-type output transistors that depend on the same signal give the circuit the ability to provide large bidirectional currents at high frequency. The implementation only requires an additional resistor and one connection change, with no additional power consumption. Simulation and experimental results of the fabricated circuit in a 0.5 µm technology show an output resistance of the proposed circuit of 12 Ω, with an enhancing factor of 60 with respect to previously reported variations.
This paper presents a novel automatic attenuator with ultra-fast transient response time. The proposed automatic attenuator combines control generation and a digital attenuator together. The control generation chain consists of a RF envelope detector, voltage comparators and a logic circuit. The state of the digital attenuator is determined by the output control signals of the control generation chain. The chip is fabricated using HuaHong 0.18 um standard CMOS technology. Measured results are offered showing that the transient response time of the whole system is less than 10 ns in the ultra-wide operation frequency range of 1 GHz∼10 GHz.
This paper presents a design-for-test structure of charge-pump phase-locked loops for on-chip jitter measurement, in which use a voltage controlled oscillator based time-to-digital converter. The structure has four key features. 1) By employing a new PFD structure to detect the time difference, it is more suitable for detecting a wide range of timing jitter. 2) The proposed DFT circuit does not need an additional jitter-free reference signal for test using the self-refereed circuit. 3) By using a new TDC structure for on-chip jitter measurement of CP-PLL, it achieves a small test area overhead. 4) The proposed DFT structure only has a minor modification on the digital part of the CP-PLL, thus it has a little adverse influence on the circuit performance. The experiment result demonstrates its possibility of detecting a timing jitter of 0.78 ps with a measurement error of 5.78%.
In this paper, the impacts of total dose radiation on the low-frequency noise and gate induced floating body effects (GIFBEs) for the 130 nm partially depleted silicon-on-insulator N-type metal-oxide semiconductors transistor with an ultrathin gate oxide have been investigated. It is shown that the second transconductance gm peak becomes smaller after irradiation when the Lorentzian-like excess noise is more pronounced. The traps induced by irradiation at shallow trench isolation/body and buried-oxide/body interface can act as the recombination centers to increase the source-body diode current, which results in the changes in the excess noise and GIFBEs.
A novel miniaturized-element frequency selective surface (MEFSS) providing a second-order bandpass response was presented and experimentally verified. The proposed structure consists of sub-wavelength inductive wire grids and a hybrid resonator composing of a two-dimensional periodic arrangement of miniaturized Jerusalem slots etched into a ground plane, which produces a miniaturized unit cell. The full-wave and equivalent circuit model simulations were performed. A prototype of the proposed second-order bandpass FSS was also fabricated and tested using a free-space measurement setup. The measurement results of this device exhibited a stable frequency response with respect to the angles of incidence up to 45°.
This paper presents the resonance transmission of a small, narrow slot in a conducting screen with two parallel wires. When a plane wave excites the slot, the aperture magnetic current is controlled by the wires connected across the slot. Parallel-wire-loaded slot resonance can occur, which is known as a transmission resonance or extraordinary transmission. In this case, the electromagnetic power transmitted through the slot with the wires is much larger than that when the wires are not present. The results show that the wires result in the maximum power transmission (resonance transmission or extraordinary transmission). The resonant frequency of a 3-cm slotted structure can be reduced from 4.56 GHz to various desired frequencies by adding the wires.