In this paper, we apply a discriminative weight training to a support vector machine (SVM) based gender identification. In our approach, the gender decision rule is derived by the SVM incorporating the optimally weighted mel-frequency cepstral coefficient (MFCC) based on a minimum classification error (MCE) method which is different from the previous works in that optimal weights are differently assigned to each MFCC which is considered more realistic. According to the experimental results, the proposed approach is found to be effective for gender identification based on the SVM.
This paper presents a hierarchical and parallel SoC (System on Chip) architecture for vision processor. The vision computing is divided into 3 task level parallel computing modules, which are vision decision, feature reorganization (or pattern generation), feature extraction. In the proposed architecture, there are two separately buses to integrate the 3 computing modules, and also the new interrupt for RISC processor to implement the synchronization between the hardware modules and software. The human-face detecting and tracking application demo has been mapped on the proposed architecture and verified on the FPGA. Architecture performance is also analyzed to show the proposed is more suitable for vision applications with higher image resolution.
Traffic forecasting plays a significant role in Network Management as well as in Congestion Control and Network Security. Accurate traffic prediction based burst and unstable point can significantly improve network performance substantially while satisfying Quality of Service (QoS) requirements. In this paper, a new traffic forecasting method of Grey theory assembled with Chaos and SVR was presented (GCSVR).In this method, we employed the chaos theory to analysis the time series, adopted the Grey theory to smooth the series, make the series has a high regularity. In the experiment section, two models for short term forecast are examined: the original SVR and the GCSVR.Through the demonstration, the precision of forecasting by the GCSVR has a better performance than the original SVR.
In this paper two ultra high speed carbon nanotube Full-Adder cells are presented. First design uses two transistors, two resistors and seven capacitors and the second one uses four transistors and seven capacitors. The first design is faster and the second one consumes less power. Simulation results illustrate significant improvement in terms of speed and Power-Delay Product (PDP).
This paper describes a microstrip-fed planar monopole antenna using Defected Ground Structure (DGS) technique. In addition, we have applied partial technique in the rectangular radiating element to achieve an ultra wide band characteristic for impedance matching. The simulated impedance band width of this antenna for S11 ≤ -10dB is about 6GHz, from 3.9GHz up to 10.8GHz. The proposed antenna's performance approximately covers the band width of ultra wide band as defined by FCC. Additional features that make this antenna attractive and viable for modern ultra-wideband system applications are its simple configuration, low profile, compactness, and low fabrication cost.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement.
The resonant mode of the wireless power transmission system is discussed to unveil a mechanism of wireless power transmission. We have analyzed electro-magnetic resonance phenomenon by using MoM to calculate input impedance, port currents, transmission efficiency, and near field distribution. We have checked that the system has two resonant frequencies, and the power transmission efficiency is maximized at those frequencies. The magnetic field distribution proves that the system has two different resonant modes. We have also considered far field to find that the higher frequency resonance is better for its high efficiency and low undesired emission.
The spatial modulation (SM) divides input data into antenna indexes and data symbols, and transmits data symbols via the specific antenna chosen by the antenna index. Soft decision technology for the SM system has not been developed, and there is room for improving the receive performance. In this paper, soft-output maximum likelihood (ML) detector for antenna index and data bit is derived to recover the desired signals by soft decision. Simulation results show that the conventional SM system with hard decision has a limitation in its performance as compared to SIMO (single-input multiple-output) system. On the other hand, the proposed SM with soft decision outperforms the SM with ML detector based on hard decision.