A dual-band bandpass filter using coplanar waveguide (CPW) has been proposed in the paper. To generate the first passband, a gap is adopted in the central strip of the CPW main transmission line, and two pairs of spiral-shaped defected ground structures (DGSs) are added to the ground planes. Then, the loaded four L-shaped slots in the central strip of the CPW main transmission line can achieve the second passband. The measured central frequencies of the dual-band bandpass filter are 3.59 GHz and 5.87 GHz. The proposed filter has good dual-passband performance and good stopband suppression.
In this paper, we propose an optimal design approach based on a concept of mosaic-like structure for achieving high performance NRD devices. In order to improve design efficiency, we employ the recently proposed two-dimensional full vectorial finite element method (2D-FVFEM) which can accurately model 3D structure of NRD as a numerical simulation method. As an optimization method, we employ either direct binary search (DBS) algorithm or genetic algorithm (GA) depending on design problems. In order to show the usefulness of our approach, design examples of crossing and T-branch waveguides are considered and high transmission efficiency greater than 99.9% for crossing waveguide and 49.8%: 49.8% for T-branch waveguide is achieved. The numerical results by 2D-FVFEM are verified by 3D-FVFEM.
Aimed at sixth-generation (6G) mobile communication applications, three fifth-order novel ultra-compact hairpin bandpass filter is proposed. Through-Silicon Via (TSV), a three-dimensional integration technology, is used to implement the arms of hairpin units, and some hairpin units consist of four arms. In this letter, the design method of the three proposed filters is introduced, and the filtering characteristics are verified by HFSS, an industry-grade simulator based on finite element method. The results reveal that the three proposed filter has the center frequency of 0.405THz, 0.3915THz, and 0.3955THz with bandwidth of 0.1THz, 0.077THz, and 0.063THz and exhibits an insertion loss of 2.0dB and return loss over 12.4dB, 13.4dB, and 14dB. The size of the three proposed filters is both 0.284 × 0.0325mm2 (1.29 × 0.148λg2).
Deep Learning (DL) training process involves intensive computations that require a large number of memory accesses. There are many surveys on memory behaviors with the DL training. They use well-known profiling tools or improving the existing tools to monitor the training processes. This paper presents a new approach to profile using a co-operate solution from software and hardware. The idea is to use Field-Programmable-Gate-Array memory as the main memory for the DL training processes on a computer. Then, the memory behaviors from both software and hardware point-of-views can be monitored and evaluated. The most common DL models are selected for the tests, including ResNet, VGG, AlexNet, and GoogLeNet. The CIFAR-10 dataset is chosen for the training database. The experimental results show that the ratio between read and write transactions is roughly about 3 to 1. The requested allocations are varied from 2-Byte to 64-MB, with the most requested sizes are approximately 16-KB to 64-KB. Based on the statistic, a suggestion was made to improve the training speed using an L4 cache for the Double-Data-Rate (DDR) memory. It can be demonstrated that our recommended L4 cache configuration can improve the DDR performance by about 15% to 18%.
This letter proposes a novel planar magic-T employing microstrip lines and a coplanar stripline (CPS) integrating a microstrip-to-CPS transition. The proposed magic-T uses a CPS instead of the slot line used in conventional planar magic-Ts to reduce the radiation loss. Defected ground structures (DGSs) are also used to suppress undesired common modes. This circuit has several attractive advantages in comparison with the conventional similar designs such as excellent amplitude and phase performance, compactness, and widely useable structure using a microstrip-to-CPS transition. The design, analysis and prototype parameters are discussed, followed by the measured and simulated results of the proposed magic-T.
This study proposes a novel microstrip patch antenna for microwave power transfer that functions as a class-F load and DC block. These functions enable a direct connection between an antenna and a power device (field-effect transistor) without using a class-F load circuit and capacitor for a DC block. In numerical simulations of a 2.45-GHz antenna, a reflection coefficient is -21.27 dB at the fundamental frequency, and a reflection coefficient and phase at the 3rd harmonic frequency are -0.99 dB and -1.4°, respectively. The simulated gain is 5.59 dBi at 2.45 GHz.