IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 19
Showing 1-15 articles out of 15 articles from the selected issue
LETTER
  • Yong-Seo Koo
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130300
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    A Low-area Low Drop-out (LDO) regulator using the body biasing technique is presented. The body biasing technique can decrease the threshold voltage and increase the drain current. The technique is applied to the error amplifier, voltage buffer and pass transistor in the proposed LDO regulator to reduce chip size and provide the proposed LDO regulator with the same performance as the conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5% at 100mA load condition. The proposed current mirror in the error amplifier and voltage buffer has about 61% smaller area at coterminous performance. The proposed LDO regulator showed about 26% smaller area, not including the bias blocks, while it showed coterminous performance and characteristics.
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  • Hongge Li, Wei Zhao, Hui Shen, Youguang Zhang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130312
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: June 28, 2013
    JOURNALS FREE ACCESS
    A novel low-power, low-noise amplifier is described for biomedical and bioengineering brain neural recording applications. The bioamplifier achieves the best power-size tradeoff compared to the previous design. By means of a new active feedback configuration, the DC offset is rejected without the large capacitors. An active differentiator with an amplifier in the feedback path places a high-pass cutting frequency in the transfer function. The midband gain consists of the passive components, and is insensitive to the mismatch of process. The bioamplifier has been implemented in the 0.35-µm 2P4M CMOS process and occupies 0.052mm2 of die area. The current consumption of amplifier is 2µA at ±1.5V supply. The bioamplifier achieves a midband gain of 42dB and a -3dB bandwidth from 13Hz to 10.5kHz. The input-referred noise is 5.7µVrms corresponding to an NEF of 3.1.
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  • Yun-Hwan Jung, Yong Sin Kim, Yohan Hong, Ju Eon Kim, Kwang-Hyun Baek
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130571
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 10, 2013
    JOURNALS FREE ACCESS
    In this paper, a low-power pipelined phase accumulator (PACC) for high-speed direct digital frequency synthesizers (DDFSs) is presented. In the proposed PACC structure, the accumulator core block and the post-skewing block are based on current mode logic (CML) design topology for high-speed operations, whereas the pre-skewing block consists of static CMOS D-F/Fs and CMOS-CML hybrid F/Fs for low-power operations. The proposed CMOS-CML hybrid F/F provides fast level conversion (CMOS to CML) by having separate current sources and it also consumes low power dissipation by sequentially activating the current sources. Simulated results show that the proposed 24-bit PACC reduces power consumption by 31% compared with a conventional pipelined architecture when input data is updated every eight clock cycles. The operating speed of the proposed PACC is 45% faster than that of the conventional pipelined PACC under the condition of the same power dissipation.
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  • Lianxi Liu, Yue Niu, Jiao Zou, Zhangming Zhu
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130579
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    It is very important for a light source that the brightness could be adjusted conveniently. A novel DC and PWM dual-mode dimming circuit for a monolithic WLED driver is proposed for the first time in this paper. It can alter flexibly the control mode between the analog (DC) and digital (PWM) dimming according to the input control signal. In the DC dimming mode, when the input DC control voltage is adjusted from 0.5V to 2.5V, the average output current can be changed from 20% to 100% of the nominal current value. While in the PWM dimming mode, the output current is proportional to the duty cycle of the input PWM signal and changed from about 0% to 100% of the nominal current value. The WLED driver with the proposed dual-mode dimming circuit has been verified in a 0.5μm HVCMOS process, and the nominal value could be set more than 1A by the external resistors.
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  • Haoran Chen, Lin’an Yang, Xiaoxian Liu, Zhangming Zhu, Jun Luo, Yue Ha ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130588
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    We report on a simulation for aluminum gallium nitride (AlGaN)/gallium nitride (GaN) resonant tunneling diode (RTD) at room temperature by introducing deep-level trapping centers into the polarized AlGaN/GaN/AlGaN quantum well. Theoretical analysis reveals that the degradations of NDR characteristics in GaN based RTDs are actually caused by the combined actions of the activation energy and the trap density. Furthermore, the trapping centers with high activation energy play a dominant role in the degradation of negative differential resistance (NDR) characteristics.
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  • Xiaofang Wu, Wei Wang, Yun Xu, Jiangnan Yuan
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130595
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    In multi-carrier transmitters, nonlinear characteristic of power amplifiers (PAs) results in intra-band distortion and inter-band distortion. The intra-band distortion exists in most single-carrier transmitters as well, and can be removed by traditional digital predistortion (DPD) techniques. However, the inter-band distortion is rather unique for the multi-carrier linearization. A channel-selective multi-cell DPD architecture which deals with the intra-band and inter-band distortion separately is used in this paper. Furthermore, a new signal injection method with particle swarm optimization (PSO) is proposed to suppress the inter-band distortion in the paper. The injected inter-band signals are firstly reconstructed by a memory polynomial DPD, and then their amplitude and phase are fine-tuned by a PSO algorithm. Simulation results show that the method restrains inter-band distortion significantly and accelerates the convergence speed of PSO algorithm.
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  • Tao Linwei, Gou Yanni
    Type: LETTER
    Subject area: Electronic instrumentation and control
    2013 Volume 10 Issue 19 Pages 20130609
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    This paper presents the design of a high-precision time keeping clock system. The system mainly consists of high-precision crystal oscillator, the accumulator (ACC), and Time Digital Convert (TDC) module. The high-precision crystal oscillator generates a pulse with the fixed cycle, and the pulse is taken as the input clock of ACC to make ACC self added according to the pre-set step. Then the overflowed signal of ACC acts as the output signal of the system’s time keeping clock. When working, the system accurately measures the period of the high precision oscillator by use of the TDC module, and then the ACC stepping values are adjusted according to the measured results. It makes the overflowed signal of ACC remain the period as a high-accuracy clock signal. The system effectively eliminates the time keeping error which comes from the error and aging of the crystal. Experiments show that the system greatly reduces the cumulative time error, and the average cumulative time keeping error is 6.5ns in one week with the time keeping mean square error of 43ns.
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  • Nam-Tae Kim
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130614
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    This paper presents a methodology for designing ultra-broadband power amplifiers (PAs) based on distributed network synthesis and offers impedance matching of a power device by parasitic absorption. For the synthesis of broadband matching circuits, transfer functions of distributed networks are provided using an equal-ripple approximation, and power device models are derived using negative-image modeling. An impedance-matching circuit that absorbs power device models can be synthesized by properly choosing the minimum insertion loss (MIL) and ripple parameters of the transfer function. As an example, distributed network synthesis is applied to the design of an ultra-broadband PA, and experiments are carried out.
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  • Kenichiro Tsuji, Toshihide Tanigaki, Kohei Hagiwara, Tomoyuki Uehara, ...
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2013 Volume 10 Issue 19 Pages 20130616
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 19, 2013
    JOURNALS FREE ACCESS
    High-speed microwave or millimeter-wave phase-shifters are the key devices in various wireless applications such as beam forming by the phased array antennas or multi-level modulation with the phase shift keying technology. In this paper, we report a simple phase control method in microwave or millimeter-wave band based on optical beat note generation using an optical phase modulator with a single light source and a narrowband optical filter. We experimentally confirmed the high stability and ultrafast phase shift keying operation of optically generated microwave signal.
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  • Qisheng Zhang, Ming Deng, Qimao Zhang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130624
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 10, 2013
    JOURNALS FREE ACCESS
    A high DC-gain low-power current recycling amplifier using positive-feedback technique is presented. In the proposed amplifier, the positive-feedback signal used to enhance the DC-gain is derived from the extra nodes created by cascoding. Positive-feedback offers the ability of obtaining a very high DC-gain, ideally infinite gain, without affecting high frequency performance and stability. Under the SMIC standard 65nm process, the proposed amplifier was implemented. Simulation results show that the DC-gain of 104.5dB is achieved with only power consumption of 25.5µA and the bandwidth is not limited.
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  • Aobo Pan, Yaping Lin, Wenjie Che, Zhiqiang You, Yonghe Liu, Jinguo Li
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130649
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    In this paper, we propose a comprehensive scheme that simultaneously achieves IP protection in both after-sale and evaluation periods. Our key idea is to build a pre-verification path into an active metering structure, with a non-functional defect purposely attached to the path, rendering any potential pirating users unwilling to risk the defective behavior of the fabricated chips. Using the MCNC’91 benchmarks, we achieve a large area-to-power ratio proving the feasibility of our scheme. At the same time, compared with a well-known metering scheme, the proposed scheme can significantly improve the robustness against brute-force attack, roughly by an average value of 27.4 per layer. The scheme can also reduce the area and power overhead by 4.4% and 11.2% on average considering an extra 5 to 10 layers.
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  • Hsin-Chuan Chen, Rong-San Lin
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130656
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    H-bridges are important driving components for consumer electronics and industry controls. They also play an important role in technologies related to DC motor control. Conventional H-bridge drivers require dead-time generation to avoid the shoot-through current resulting from both upper and lower power transistors being turned on concurrently. Unlike the conventional H-bridge driver, this paper proposes an H-bridge driver based on a complementary MOSFET type using gate bias, without a dead time generator, to improve its driving efficiency. Moreover, this proposed H-bridge driver also has a reduced hardware complexity.
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  • Shijian Guo, Jian Su, Gang Sun, Zhiyong Zhao, Zengping Chen
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130657
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    A new method named Digital Phosphor technology (DPX) is presented for real-time spectrum analysis and signal detection. The process of generating the 3-D spectrum in the DPX system is analyzed, and a practical DPX system is designed and implemented. The maximum effective bandwidth is 500MHz, and the signals are sampled directly in radio frequency (RF) with 1.2GHz sampling rate. The main data processing module employs dual-FPGA architecture. 65,535 frames of frequency waveforms are continuously processed and accumulated in one DPX image within 100ms. The experimental results have indicated that the 3-D spectrum of DPX greatly improves the capabilities of signal discovery, capture and analysis, and the DPX system is adapted to real-time spectrum analysis and signal detection.
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  • Omar A. Barrera, Dong Hyun Lee, Nguyen Manh Quyet, Viet Hoang-The, Hyu ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 19 Pages 20130665
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 11, 2013
    JOURNALS FREE ACCESS
    A dual-feed circularly polarized antenna with built-in harmonic-rejection capabilities is presented for the first time. The square patch antenna has been designed at 5.8GHz and incorporates both circular polarization and harmonic-rejection in a single design, thus eliminating the need of a low-pass filter. A comparison among the proposed antenna, a simple square patch antenna, and a truncated square patch antenna is performed to evaluate the capabilities of the proposed design. The realized antenna exhibits a reflection coefficient of -1.92dB at the second harmonic frequency of 11.6GHz, and circular polarization for elevation angles in the range of -600 to 600, well suited for a rectenna in wireless power transfer applications.
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  • Sun-Wook Choi, Chong Ho Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 19 Pages 20130673
    Published: October 10, 2013
    Released: October 10, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    Recently, use of high-throughput data with highdimensional feature space such as images and microarrays have increased significantly. Therefore, a fast and efficient method to process these data is required. In this paper, we propose a novel semi-naive Bayes classification method based on stochastic discrimination theory and implement it in hardware. The hardware implemented on a FPGA with massively parallel computation enables fast and efficient processing, because the algorithm of the proposed method is very suitable for parallel computation. The implemented hardware takes 0.378µs at 106MHz clock to process given one test data. In addition, we evaluate the performance of the proposed method through experiments on various datasets. In the experimental results, our proposed method shows competitive performance compared with conventional machine learning methods.
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