An improved frequency measurement method using FPGA and TDC (time-to-digital converter) is proposed, and its error analysis is carried out. Instead of measuring more precise counting values of equal-precision frequency measurement, this method obtains the converted frequency indirectly by accurately measuring the time of multiple measured signal cycles. It significantly improves the accuracy of the frequency meter in atomic magnetometer. The method is capable of eliminating the ±1 error of reference signal counting of equal precision frequency measurement method, as well as avoiding the limitation that the measurement range of TDC cannot reach 0. With this method, a prototype of the frequency meter is implemented with very small size. Tests show that the prototype achieved 0.0042 Hz precision and 0.00056 Hz standard deviation in the frequency range of 70 kHz to 350 kHz at the output rate of 10 Hz.
In this paper, an integrated four port DC-DC converter with bidirectional power transfer capability is proposed for connecting two photovoltaic sources with an energy storage element to a dc load. This converter achieves high power density due to its integrated structure and device sharing feature among the ports. Adopted PWM and secondary side phase-shifting control eliminates the circulating current and its associated conduction losses and minimizes the current ripple at input ports. Further, it simplifies the complexity of control by decoupling the control variables of input and output ports. Working of the converter under different operating conditions are verified with a 500-W experimental prototype.
A compact tri-band bandpass filter (BPF) with high selectivity and wide stopband performance is developed based on a modified stub-loaded quarter-wavelength stepped-impedance resonator (SL-SIR). The modified SL-SIR has flexibly controllable resonance modes under different schematics of the loaded stubs, from which, a tri-mode case is chosen to design a tri-band BPF with controllable centre frequencies and bandwidths. Furthermore, up to ten transmission zeros are created by introducing two source-load couplings simultaneously, which not only enhance significantly the selectivity of three passbands, but also widen greatly the stopband of the BPF. The tri-band BPF, operating at 1.27, 3.65, and 5.20 GHz, is designed and fabricated, and its measured responses are in good agreement with the simulated ones.
Analog filter implementation of continuous wavelet transform is considered as a promising technique for on-line spike detection applied in wearable electroencephalogram system. This Letter proposes a novel method to construct analog wavelet base for analog wavelet filter design, in which the mathematical approximation model in frequency domain is built as an optimization problem and the genetic algorithm is used to find the global optimum resolution. Also, the Gm-C filter structure based on LC ladder simulation is employed to synthesize the obtained analog wavelet base. The Marr wavelet filter is designed as an example using SMIC 1 V 0.35 µm CMOS technology. Simulation results show that the proposed method can give a stable analog wavelet filter with higher approximation accuracy and excellent circuit performance, which is well suited for the design of low-frequency low-power spike detector.
This paper presents a novel bit-serial semi-systolic array structure to simultaneously execute modular multiplication and squaring operations in GF(2m). The architecture is explored by using a systematic methodology based on the proper choice of the scheduling and projection vectors applied to the algorithm dependency graph. The explored architecture has the advantage of sharing the data-path between the two operations, and hence it leads to saving more space compared to the case of using a separate data-path for each operation. Also, the simultaneous calculation of both operations significantly decreases the execution time required to perform modular exponentiation operation, as it mainly depends on these two core operations. Complexity analysis indicates that the developed bit-serial semi-systolic array structure outperforms the latest exiting competitor bit-serial systolic and non-systolic structures in terms of area-time (AT) by at least 24%. This makes the proposed structure more appropriate for use in resource-constrained cryptographic processors.
A new precise current mode bandgap voltage reference with TlnT compensation of non-linear temperature is proposed. By using the voltage difference of two transistors working in different current states, the nonlinear compensation term of TlnT is generated. At the same time, the optimal high-precision reference voltage source is obtained by using the method of piecewise compensation. This design with 0.18 µm CMOS process is achieved an ultra-low temperature coefficient (TC) of 0.918 ppm/°C from −40 °C to 125 °C. The minimum required supply voltage is 1.8 V and the current consumption is 23 µA at 25 °C. And the line regulation performance is 0.0055%/V at 25 °C with a supply voltage range of 1.8 V to 3.6 V.
A dual-band low-profile substrate integrated waveguide (SIW) dual-dumbbell-shaped-slot-fed (DDSSF) patch antenna is presented in this letter. The antenna is designed using the dual-dumbbell-slot feeding structure in SIW and two patches to radiate. And it achieves two passbands by exciting two modes of dual dumbbell-shaped slots (DDSSs). The first impedance bandwidth is 4.1%, the second one is 10.0% and gains up to 6.7 dBi and 7.4 dBi, respectively. Furthermore, the two bands can be separated from each other and the cross-polarization level is below −30 dB. The simulation and measurement results of the proposed antenna are in good agreements.
An 8-port MIMO antenna system covering the band of 3–6 GHz for the 5G MIMO mobile handset applications is proposed. The antenna element consists of an open-slot antenna and a T-shaped feeding strip. Also, an L-shaped strip is adopted to improve the impedance bandwidth and achieve miniaturization simultaneously. The measured results show that wide impedance bandwidth, high isolation (>11 dB), high efficiency (>40%) and lower ECC (<0.1) are realized. Finally, the hand-grip effects are investigated by simulation to verify its capability for the industrial applications.
Convolutional Neuronal Networks (CNN) implementation on embedded devices is restricted due to the number of layers of some CNN models. In this context, this paper describes a novel architecture based on Layer Operation Chaining (LOC) which uses fewer convolvers than convolution layers. A reutilization of hardware convolvers is promoted through kernel decomposition. Thus, an architectural design with reduced resources utilization is achieved, suitable to be implemented on low-end devices as a solution for portable classification applications. Experimental results show that the proposed design has a competitive processing time and overcomes resource utilization when compared with state-of-the-art related works.
By combining the functions of a poly phase filter and a variable gain amplifier, a 2nd order active complex filter is proposed in this paper for 5G and other broadband applications. Thanks to the TIA based structure, the complex filter has an operating speed up to 2.3 GHz and a variable voltage gain of 0–20 dB. Its center frequency is programmable from 500 MHz to 1.85 GHz by integrating an on-chip capacitor tank. An image rejection ratio of higher than 17 dB is achieved when its gain is 14 dB for all center frequency settings, consuming less than 40.6 mW from a 1.4 V supply. Fabricated in a 65 nm CMOS process, the core circuit area is 0.25 mm × 0.2 mm. To the best knowledge of the authors, this work is the first published GHz active complex filter, advancing the state-of-the-art.
This paper presents a wideband slot antenna with filtering response based on split-ring resonator (SRR). A T-shaped coplanar waveguide (CPW)-fed is utilized to excite the SRR and the slots near the SRR. Hence, multiple current paths of different lengths are induced, making the proposed antenna have wideband performance. Additionally, thanks to the symmetry of the proposed antenna, high cut-off frequency is achieved in realized gain response. To obtain the low cut-off frequency, two modified U-shaped stubs are introduced near the feeding line. Therefore, the proposed antenna could realize filtering function without any extra circuits and matching stubs.
To minimize the characteristic variation of SPADs (Single-Photon Avalanche Photo Diodes) with bias, a current mirror based quenching bias circuit is implemented and tested for Single Photon Detection. With the proposed quenching bias circuit, the operational bias variation of SPADs is successfully reduced. A SPAD and quenching bias circuit are integrated in a 43 µm × 43 µm area to make a micro pixel. The optimized bias circuit maximizes the photon detection area to have more than 50% fill factor. This paper is based on a 0.18 µm standard CMOS process with thick gate oxide option.
We present a wavelength-tunable ultrafast optical switch using a nonlinear optical loop mirror (NOLM), which has a low walk-off characteristic between the signal pulse and the control pulse thanks to the use of a dispersion-flattened highly nonlinear fiber. A 400-fs switching speed and an extinction ratio of >32 dB were obtained from 1528 to 1565 nm. The NOLM was applied to the 320 to 40 Gbaud demultiplexing of DQPSK Nyquist pulse signals, and error-free operation was achieved over the entire C-band.