IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 4
Showing 1-13 articles out of 13 articles from the selected issue
LETTER
  • Yasar Amin, Yi Feng, Qiang Chen, Li-Rong Zheng, Hannu Tenhunen
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130003
    Published: February 18, 2013
    Released: February 18, 2013
    JOURNALS FREE ACCESS
    We demonstrate for the first time an RFID tag antenna which itself is humidity sensor and also provides calibration functionality. The antenna is comprised of T-matching network and horizontally meandered lines for impedance matching and reliable near-field communication. The novel contour design provides humidity sensing, and calibration functions whilst concurrently acts as a radiating element along with quadrangular capacitive tip-loading with covered middle portion for far-field communication. The inkjet printed prototypes of the antenna provide effective ambient humidity sensing while demonstrating stable RFID communication. The antenna has a compact size of 1.1 × 10.2cm for 902-928MHz band.
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  • Wang-Soo Kim, Woo-Young Choi
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130030
    Published: February 18, 2013
    Released: February 18, 2013
    JOURNALS FREE ACCESS
    This paper presents a 10-Gb/s low-power adaptive continuous-time linear equalizer, which automatically determines the optimal equalization condition by searching for the equalization coefficient producing the largest peak value in histograms obtained with asynchronous under-sampling. To reduce the power consumption, the integrated digital controller turns off the circuit blocks used for the adaptation process once adaptation is complete. A prototype equalizer realized in 65-nm CMOS technology consumes 4.66mW during adaptation and 2.49mW after adaptation. For 10-Gb/s 231−1 PRBS data transmitted over 40-cm FR4 PCB trace, our equalizer achieves less than 10−13 BER and 26.6ps peak-to-peak jitter.
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  • Dong Wang, Pengju Ren, Leibo Liu
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120879
    Published: February 19, 2013
    Released: February 19, 2013
    JOURNALS FREE ACCESS
    This paper presents a high-throughput fixed-point complex divider which uses four pipelined CORDIC units to transform and divide complex numbers in Polar coordinates. By persevering the macro-angle for CORDIC rotations in redundant form and developing an optimized pipelining structure, the FPGA based implementation achieves a 9× advantage on throughput over the best design reported. In addition, the final error is guaranteed within 1ulp (unit in last position). Thus the proposed complex divider is highly suitable for accelerating DSP applications with high precision numerical accuracy requirements.
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  • Xiaoming Yang, Tianqian Li, Yu Cai, Jun Wang, Changjiang Chen
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130057
    Published: February 19, 2013
    Released: February 19, 2013
    JOURNALS FREE ACCESS
    A high voltage silicon-on-insulator (SOI) LDMOS with an accumulated charges layer (ACL) for double enhanced dielectric electric field (DEDF) is proposed. The electrons and holes can be accumulated in the ACL with a back-gate bias in off-state. These charges can enhance the dielectric field in the buried oxide (BOX) layer under the source and drain for improving breakdown voltage (BV). Moreover, the ACL can also enhance the reduced surface field (RESURF) effect. Compared with the conventional SOI and Shield-Trench SOI, BV of the DEDF SOI can achieve 1163V at 1µm BOX and 550V back-gate voltage.
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  • Seongjoon Do, Eunji Lee, Taeseok Kim
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130018
    Published: February 22, 2013
    Released: February 22, 2013
    JOURNALS FREE ACCESS
    In multi-channel architecture SSDs, as two or more flash memories can operate independently via different channels, I/O operations are actually performed in a cluster unit consisting of several pages. This paper proposes a novel write buffer replacement policy that fully exploits such high parallelism of SSDs and leads to better I/O performance. Our proposed scheme evaluates buffers in a cluster unit by intelligently aggregating the re-reference probability of pages in a cluster. The pages belonging to the least valuable cluster are evicted together when the replacement is needed. This replacement policy efficiently takes both the parallel architecture of SSDs and the temporal locality of I/O workloads into consideration, and thus achieves better I/O performance of SSDs. Through the trace-driven simulations, we show that our scheme improves performance up to 25% in terms of write throughput for common workloads.
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  • Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao ...
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130022
    Published: February 22, 2013
    Released: February 22, 2013
    JOURNALS FREE ACCESS
    This paper proposes a low voltage CMOS nano-ampere current reference circuit and presents its performance with circuit simulations in 180-nm technology. The proposed circuit consists of bias-voltage, current-source and offset-voltage sub-circuits with most of MOSFETs operating in subthreshold region. Simulation results show that the circuit generates a stable reference current of 110-nA in supply voltage range of 0.8-1.8-V with line sensitivity of 9250ppm/V. The proposed circuit is useful for composing a voltage reference circuit for ultra-low power applications.
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  • Bonghyuk Park, Jaeho Jung, Kwangchun Lee
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120929
    Published: February 26, 2013
    Released: February 26, 2013
    JOURNALS FREE ACCESS
    A fully integrated pulsewidth modulator for Class-S power amplifiers is presented. It consists of a triangular signal generator, a comparator and output buffer. The HBT BiCMOS design of PWM circuit is applied to the LTE frequency range, which converts digitally modulated 955MHz RF carrier with 2.87GHz sampling clock. This PWM shows an EVM 6.6%, a differential output voltage swing 1.35Vp-p with 62.7mA dissipating at 3.3V power supply.
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  • A. Sahafi, J. Sobhi, Z.D. Koozekanani
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120945
    Published: February 26, 2013
    Released: February 26, 2013
    JOURNALS FREE ACCESS
    This paper presents a simple Pico Watt reference circuit with the output voltage of 263.1mV using sub-threshold operation of MOSFETs at supply voltage of 0.7V. Proposed circuit consumes merely 400pW of power at room temperature and it is designed using standard TSMC 0.18µm technology. Reference voltage is provided by subtracting the 0°C threshold voltage of MOSFETs. The simulation results show voltage variation of 0.32mV/V for supply voltage from 0.7V to 2.5V and about 0.4mV of temperature variation in the range of -40°C to 120°C. The active area of the proposed circuit is 500µm2. Our device would be suitable for use in passive RFIDs, WSN applications and all other power-aware SOCs.
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  • Rui Chen, Changle Li, Jiandong Li, Yanjun Ma, Cong Li
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130060
    Published: February 26, 2013
    Released: February 26, 2013
    JOURNALS FREE ACCESS
    A new minimum-total-mean-square-error (MTMSE) criterion based vector perturbation precoder is proposed for multi-user multi-stream MIMO downlink, which has much lower computational complexity and slightly better BER performance than the traditional MTMSE-MUMS-VP precoder we proposed before. Furthermore, the proposed precoder is verified on a Xilinx Virtex-4 FPGA at 400MHz. Many slices resource can be saved due to the reduction of complexity, and with 16QAM constellation the data throughput is up to 12.8Gbit/s in a {2,2,2,2} × 8 MIMO configuration.
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  • Yuliang Chang, Ling Wen, Huanyao Dai
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120854
    Published: February 27, 2013
    Released: February 27, 2013
    JOURNALS FREE ACCESS
    A new method of target detection for polarimetric radar in the presence of strong active jamming is proposed. Based on analysis of the polarization characterizations of the signals received by polarimetric radar, the target detection is achieved through testing on the polarization information. Comparing with the traditional method of target detection made in time-frequency domain, the detection performance of the new method is improved because the influence of the strong active jamming is avoided. The performance of the new method is analyzed by simulation experiment.
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  • Hong-Yeol Lim, Gi-Ho Park
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120971
    Published: February 27, 2013
    Released: February 27, 2013
    JOURNALS FREE ACCESS
    Three-dimensional (3-D) integration technology provides various architectural opportunities including huge memory bandwidth. This paper proposes versatile stream buffer architecture to work as a secondary victim cache as well as the conventional stream buffer. The versatile stream buffer utilizes empty spaces to exploit massive memory bandwidth provided by 3-D integration technology and to reduce memory access frequency. Performance evaluation results show that the proposed mechanism with a 16KB stream buffer and a 4KB victim cache can achieve better performance than the conventional L2 cache with the capacity of 256KB and 2MB by 10% and 3%, respectively. The proposed mechanism reduces the miss rate by about 12% more than the conventional L2 cache with the capacity of 256KB.
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  • Liu Jing
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20120959
    Published: February 28, 2013
    Released: February 28, 2013
    JOURNALS FREE ACCESS
    In contrary to the existing work related with compressed sensing based STAP technique, which adopts the original sensing matrix, the proposed noise driven compressed sensing method is to construct a new sensing matrix with weak coherence through incorporating the measurement noise. The proposed method tries to build an equivalent system of the classical model in compressed sensing, resulting in an equivalent sensing matrix. Inspired by the idea that low coherence guarantees the reconstruction of the sparse vector with large probability, the equivalent sensing matrix is updated iteratively in a Markov chain Monte Carlo (MCMC) based framework to reduce the large coherence between a set of specific columns in the original sensing matrix. At the same time, the proposed method tries to preserve most of the information of the original sensing matrix via adjusting a noise related matrix. The simulation results show that the proposed method obtains much less average reconstruction error compared with the existing compressed sensing based STAP methods, and it is also very efficient when coping with measurement noise with low SNR.
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  • Chun Wei Lin, Bing Shiun Hsieh, Ying Xu Tsai
    Type: LETTER
    2013 Volume 10 Issue 4 Pages 20130070
    Published: February 28, 2013
    Released: February 28, 2013
    JOURNALS FREE ACCESS
    This paper presents a dimming technique for light emitting diode (LED), which improves the resolution of luminous intensity, luminous efficiency and extends the life of device. The presented method quantifies corresponding variation from light sensor into binary representation by a pulse width modulator (PWM) and multilevel generator. After that, a digital filter is further used to perform interpolation on converted binary codes enhancing the length of signal. Through controlling the binary-weighted current regulation, the presented method provides 8-bit resolution on adjusting luminous intensity.
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