Networks-on-chip (NoC) is a major contributor to the power consumption in modern many-core processors, especially the router comprising large number of virtual channel (VC) first-in-first-out (FIFO) buffers. In this paper, we propose three buffer designs that leverage the unique serial access mechanism, non-volatility and high density of Domain-Wall Memory (DWM) to replace conventional SRAM based buffers in NoC router. Experiments demonstrates that the proposed DWM designs can achieve considerable improvement in area and power efficiency. The best performing proposed approach shows 36.1% (24.2%) area and 55.1% (24.5%) power saving over conventional SRAM (STT-MRAM) based designs respectively without performance degradation.
This study proposes a Ka-band high-performance microstrip array antenna having a planar array front-end and strip-line back-end. 10×4 hybrid-fed rectangular patches with Taylor-synthesized excitation is adopted to form weighted patterns. Preferable symmetrical patterns are obtained covering 34.5-35.5 GHz working band due to the symmetric feeding arrangement. The measured reflection coefficient is lower than -10 dB, and peak co-polarization gain and first side-lobe level are better than 19 dB and -17 dB, respectively. Additionally, the strip-line back-end ensures an ideal front-to-back ratio of approximately 40 dB. The measurement results coincide with the simulation results, proving the immense prospect of our design in airspace detection or other applicable scenarios.
This paper deals with the high-speed switching operation of a main circuit when using a silicon carbide (SiC) complementary metal-oxide semiconductor (CMOS) and power module for the high-speed drive. When using the developed power module and SiC CMOS gate buffer, we experimentally achieved the turn-on and turn-off switching speeds of about -100 and 80 V/ns at a DC bus voltage of 600 V and a load current of 20 A. Based on the I-V characteristics of the developed SiC CMOS and the gate charge of the SiC power MOSFET, the approximate switching time was calculated.
In this paper, the degradation of low-frequency (LF) noise under different RF stress conditions in nMOSFETs has been reported and compared with the conventional DC stress condition. LF noise increases after RF stress and the increment of noise under RF stress at a large Vgs value is bigger than that caused by DC stress. The change in LF noise intensity under RF stress raised more rapidly at large Vgs values than that at small Vgs values, which are contradictory to LF noise performance after DC stress. The influence of the input power and frequency of stress on LF noise has also been investigated separately. As the stress input power or frequency increases, the increment of noise intensity rises as well. The γ decreases as the growth of the stress input power or frequency, and the values of γ are below 1 after 18 GHz RF stress. The results provide experimental verification that the interface traps generated by RF stress play a major role in the degradation of LF noise.