This letter presents a novel bus coding technique suitable for a bus with OR chaining that requires data parking at the end of data transmission. Based on the fact that the data parking state is known a priori, the proposed technique encodes the last sequential data value by jointly considering two switching activities, one that occurred due to a change in valid data values and the other that will be subsequently occurred by data parking. Compared to the conventional bus coding scheme that picks a codeword that minimizes only the former, the proposed technique can achieve >3% additional saving of switching activity in average. Evaluation results based on 22-nm CMOS technology show that the proposed scheme, even with its higher encoding energy, can obtain the lower total energy for >0.59mm bus length in comparison with the conventional data bus invert technique.

A wideband RF logarithmic power detector with large dynamic range is presented in this work. The power detector fabricated in 180-nm SiGe process employs the successive approximation technique over a 6-stage cascaded amplifier chain. A cross-coupled cascode amplifier architecture is proposed to expand bandwidth up to 8GHz. With a temperature compensation circuit and a DC offset compensation loop, the detector provides consistent logarithmic performance at different temperatures in band, which can be applied in highly reliable RF systems. The measured input dynamic range is larger than 50dB in 1MHz∼8GHz with less than ±1dB error and 55dB at 8GHz with less than ±3dB error. The measured temperature drift is less than ±1.0dB at 5GHz over the temperature range from -40 to 85℃.

This letter presents a low voltage high-output-swing gate-switching charge pump (CP) used in phase-locked loops (PLL). The current self-matching technique is proposed to dynamically bias the gate of the current source transistors corresponding to output voltage fluctuation, keeping charging and discharging currents constant. To overcome the voltage margin issues under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is proposed as the error amplifier of the negative feedback loop. The current mismatch of less than 2% is realized in the voltage range from 0.05V to 0.55V. A prototype of the proposed CP is designed and fabricated in TSMC 28nm CMOS process under a 0.6V supply voltage. Charging and discharging currents are designed to be identical during the entire reset impulse. The measured reference spur is less than -59.4dBc.