Two novel PSRR characteristic enhancement technologies based on the voltage reference (VR) is presented: Double-reference PSRR stacking technology (DRPST) and Pre-regulated-current technology (PRCT). The above two novel technologies are explained by designing two voltage reference structures. The voltage reference is obtained by a depletion NMOS and an enhancement NMOS. Structure I employs DRPST compared with the traditional Pre-regulated-voltage technology (PRVT) to improve the PSRR. Structure II uses PRCT composed of DRPST and improved Pre-regulated-voltage technology (IPRVT) to improve PSRR. The above two structural reference sources are simulated in standard 0.18µm CMOS process. When the output reference is 810mV, the PSRR of VR obtained in Structure I is -140dB@1KHz at TT corner with the line sensitivity: LS =0.023%/V, the temperature coefficients: TC=4.2ppm/°C; The PSRR of the Structure II is -114dB@1KHz at TT corner with LS =0.013%/V, TC =7.5ppm/°C.
This paper analyzes the power decoupling performance of the mismatched split-capacitor half-bridge circuit, and reveals the mechanism of fundamental harmonic generation in the circuit through the mathematical model of the decoupling circuit established. In order to solve this problem, firstly, this paper proposes a control strategy of introducing DC bias coefficient on the basis of instantaneous voltage control of split capacitor C1. Secondly, using instantaneous voltage of capacitor C1 as control quantity can better realize voltage tracking control effect, with fast response speed and simple control. Finally, the effectiveness of this control strategy is verified by experiments.
This paper presents a digital foreground calibration method intended for Successive Approximation (SAR) Analog-to-Digital Converters (ADCs). It begins by investigating the Integral Non-linearity (INL) and Signal to Noise Ratio (SNR) degradation with 1% capacitor mismatches. Later, it compares the INL and SNR for the ADC with and without using the proposed calibration method, and with various levels of capacitor redundancy and mismatches. The MATLAB simulation results show the proposed method can improve the ADCs’ INL and SNR by 0.8 LSB and 5.8dB, on average for 100 runs, respectively, when 1% capacitor mismatches are present. Measurement results of the 15 column SAR ADCs indicate that the INL and the SNR can be improved by 1 LSB and 2dB, respectively, using the proposed calibration method.
There are two research hotspots for improving performance and energy efficiency of the inference phase of Convolutional neural networks (CNNs). The first one is model compression techniques while the second is hardware accelerator implementation. To overcome the incompatibility of algorithm optimization and hardware design, this paper proposes HFOD, a hardware-friendly quantization method for object detection on embedded FPGAs. We adopt a channel-wise, uniform quantization method to compress YOLOv3-Tiny model. Weights are quantized to 2-bit while activations are quantized to 8-bit for all convolutional layers. To achieve highly-efficient implementations on FPGA, we add batch normalization (BN) layer fusion in quantization process. A flexible, efficient convolutional unit structure is designed to utilize hardware-friendly quantization, and the accelerator is developed based on an automatic synthesis template. Experimental results show that the resources of FPGA in the proposed accelerator design contribute more computing performance compared with regular 8-bit/16-bit fixed point quantization. The model size and the activation size of the proposed network with 2-bit weights and 8-bit activations can be effectively reduced by 16× and 4× with a small amount of accuracy loss, respectively. Our HFOD method can achieve 90.6 GOPS on PYNQ-Z2 at 150MHz, which is 1.4× faster and 2× better in power efficiency than peer FPGA implementation on the same platform.
This paper presents a miniaturized broadband monopole AOC (antenna on chip) for W-band. The AOC miniaturization is achieved by a hexagonal grid at the top layer M6 and a capacitive AMC (artificial magnetic conductor) at the bottom layer M1 based on a 130nm CMOS process. First, the reflection phase of different modes is analyzed using electromagnetics simulation. Secondly, the axial size of the AOC with AMC is further reduced by 16.2% (compared to a straight monopole antenna with AMC) by using a hexagonal grid, and the impedance is optimized by analyzing the grid angle. The proposed miniaturized monopole antenna has the size of 367um×194.2um (0.1λ0×0.052λ0) at 81GHz. Measurements show that the antenna has an impedance bandwidth of 31.5% (75-103GHz) and a peak gain of -0.35dBi at 85GHz. The proposed antenna has the smallest reported size and can be applied to W-band FMCW radar system on chip.
Edge intelligence (EI), as a combination of artificial intelligence (AI) and internet of things (IoT), is the key to realize an interconnected world of everything. EI needs to process the data collected by edge devices locally. For edge devices with insufficient computing power, a near data computing (NDC) system can provide local computing capability by adding a co-processing unit near the memory. NDC systems are extensively studied focused on the optimization of the hardware architecture but lack of universal and transparent system support. Meanwhile, we notice that non-volatile memory (NVM) plays an important role in edge intermittent computing. In this article, we propose a novel in-memory processing file system (IMPFS) based on NVM to provide general support for NDC system running on edge devices. IMPFS uses standard file system interfaces and is optimized for NVM and AI application management. To verify the IMPFS, a prototype system is designed. The results showed that the IMPFS can not only provide universal support for EI but also further improve the processing speed by reducing the redundant software overhead.
Optical fiber has been widely used for security monitoring due to its sensitive phase and amplitude reacting from external vibration. However, it is difficult to extract the intrusion characteristics of optical fiber and identify intrusion in windy conditions. To solve this problem, we introduce a state space model for the optical fiber detection system and propose two intrusion detection methods, e.g., estimating noise variance based on system identification and calculating cross output reconstruction error. The accuracy and effectiveness of the two methods are demonstrated by field data collected in windy environment. The results show that the proposed methods outperform compared existing methods in both performance and robustness.
This letter presents a cryogenic digital-to-analog converter (DAC) for controlling qubits in a large-scale quantum computer. The capacitor arrays composing a charge-redistribution DAC are miniaturized by effectively utilizing the cryogenic characteristics of extremely low noise and leakage. Furthermore, capacitor mismatches due to their small size are automatically corrected by a newly proposed calibration technique with a small area-overhead. Fabricated in 40 nm CMOS and measured at cryogenic temperature, the prototype 11-bit DAC achieved a very small area of 0.3mm2 and low power consumption of 5.8μW, while realizing a non-linearity error within +/-2LSB.
This letter presents a linear K-band voltage-controlled oscillator (VCO) with a Gilbert frequency multiplier. Three pairs of varactors form a varactor compensation topology to broaden the linear frequency range and improve the VCO linearity. The varactors are tuned by two control voltages so that the frequency can be tuned in a wide range continuously. A Gilbert cell-based frequency multiplier is implemented to achieve the desired frequency with low phase noise. Fabricated in 0.13μm CMOS technology, the total area of the proposed VCO is approximately 0.28mm2. This VCO achieves a tuning range of 21.4 to 25GHz (15.5%), and a linear tuning range between 0.5V to 1.8V control voltage, the mismatch of the VCO gain is only 9.1% in the linear tuning range. The output phase noise reaches -75.13dBc/Hz at 100kHz offset frequency and -108.53dBc/Hz at 1MHz offset frequency from the 24.2GHz carrier frequency, respectively.
In this letter, a 30MHz-3GHz 1W ultra-broadband stacked power amplifier (PA) fabricated in 0.25um GaAs pHEMT technology process is presented. By inserting an RC network between the bridge-T input lossy matching network and the stacked-FET, the stability enhancement and input standing wave ratio (SWR) optimization are achieved with high frequency gain compensation. Based on the performance simulations of the stacked-PA with various normalized output load impedance, an optimal output matching method is applied, which obtains 31±1dBm output power at 15dBm input power, while the peak PAE achieves 60.2% at 30MHz and the PAE larger than 35% over all of the operating frequency band. Moreover, the size of MMIC PA achieves 1.51mm2 with 50Ω input and output matching.
A dual-source energy harvesting system based on self-triggered flyback converter (STFC) topology is proposed to extract energy from piezoelectric transducers (PZT) and thermoelectric generators (TEG) simultaneously. The passive module of the STFC circuit can extract energy from the PZT and TEGs at the peaks of PZT voltage. The active module can be triggered to extract energy from the TEGs efficiently during the off-peak time of the PZT voltage and can realize the maximum power extraction of TEGs. The measurement shows that the output power of the STFC circuit is 3.72 times of that without TEG.