This paper presents a high performance sparse matrix-vector multiplication (SpMV) accelerator on the field-programming gate array (FPGA). By exploiting a hardware-friendly storage scheme, named as Variable-Bit-Width Coordinate Block Quasi Compressed Sparse Row, the redundant computation and memory accesses can be reduced greatly through the nested block compression and variable-bit-width column-index encoding schemes. Based on the proposed compression scheme, a deeply-pipelined SpMV accelerator is implemented on a Xilinx Virtex XC7VX485T FPGA platform, which can handle sparse matrices with arbitrary size and sparsity pattern. Experimental results show that the proposed design can gain higher performance for most of the tested matrices and improve the utilization of the memory bandwidth up to 13×, compared with the previous works on the Convey platforms (HC-1 and HC-2ex) and Nvidia Tesla S1070 GPU platform.

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Sparse matrix-vector multiplication (SpMV) represents the dominant cost in sparse linear algebra. However, sparse matrices exhibit inherent irregularity in both amount and distribution of none-zero values. This harnessed the tremendous potential of Single Instruction Multiple Data (SIMD) architectures, which is widely adopted in nowadays data-parallel processors. To improve the performance of SpMV, we proposed the Balanced SCT (B-SCT) method. The cornerstones are composed of the balanced-aware compression scheme and the on-the-fly data re-order structure. Our simulation results show that the B-SCT method provides an average speed-up of 130% over the commonly used CSR method, and 83% over the SIMD-oriented SCT method.

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This paper presents a novel design of low-frequency coded ground penetrating radar (GPR) for deep detection. In order to increase the signal-to-noise ratio (SNR) of the returned signals of the deep targets, 2048 groups of Golay codes with 8 chips and 1 kW peak power are radiated by the transmitter. The receiver has two receiving channels, the first channel with a gain of 10 dB is used to obtain the reference signals, and the second channel, which has a maximum gain of 50 dB for deep targets and a minimal gain of −10 dB for shallow targets, is designed to receive the radar echoes. The real-time impulse compression is computed with 280 DSP48 slices of FPGA in parallel. Two pairs of fiber modules are used for synchronization between the transmitter and receiver. The transmitter and the receiver are discussed in detail. The experimental results show that the proposed low-frequency coded GPR has good detection performance for deep detection applications.

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Using the concept of common components, this letter shows that field multiplication and squaring over GF(2^m) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.

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The OCC control approach for single-phase boost PFC rectifier without the requirement of input voltage sensing or complicated two loops compensation design could result in high power factor, low harmonic input current ingredients operation over universal loads in continuous conduction mode. The trialing triangle modulation adopted in this paper makes the acquisition of the average input current an easy process. The implementation of the controller is based on boost topology power circuit with low speed, low resolution A/D converters and economic FPGA development board. Experimental results demonstrate that the proposed PFC rectifier could get PF value up to 0.999 and the minimum THD down to 1.9% by a 120 W prototype.

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A simple and novel predictive duty cycle control strategy for boost PFC converter is proposed. The duty cycle is calculated based on input current, input voltage and output voltage for every cycle. The operating principles and control scheme are analyzed and discussed in detail. Experimental results of a 120 W boost power PFC prototype point out that high power factor and low input current THD are achieved over the entire output power range using proposed control strategy. The results prove to be satisfactory.

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This paper focuses on a development and an evaluation of high-speed gate drive circuit for SiC power MOSFET by GaN HEMT. The increasing requests to SiC power devices face to the difficulty of the gate drive because of the mismatching between device parameters and conventional driving circuits for Si power devices. Up to now, high frequency switching is the main target of logic and radio applications of active devices. The drive circuit of power devises has not been considered at the switching over MHz. Moreover, p-type SiC and GaN power devices are still not in our hand in spite of the development of n-type device. Therefore there are difficulties in the design of symmetric circuit structure to avoid the management of ground setting. This paper proposes a gate drive circuit applied GaN devices for high-speed switching of an SiC MOSFET. The proposed circuit is designed for the operation of SiC MOSFET at 10 MHz. The feasibility is confirmed through a simple switching circuit.

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This letter presents a frequency-tunable, dual-function, microwave filter with both bandpass and bandstop functionalities. The filter uses a single switch to change the functionality minimizing the insertion loss, and it can replace a traditional filter bank structure that contains two filters and two switches. Frequency-tunable substrate-integrated waveguide (SIW) resonators are adopted in this filter design. Measured results show that both bandpass and bandstop responses can be tuned from 3.0 GHz to 3.6 GHz. The measured minimum insertion loss at the center frequency is 1.1 dB for the bandpass mode and the attenuation at the center frequency is greater than 40 dB over the entire frequency tuning range.

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This paper describes the synthesis method of uniformly excited unequally spaced planar array with maximum beam collection efficiency (BCE, i.e., the ratio between the power radiated over a target region and the whole transmitted power) using Particle Swarm Optimization (PSO) algorithm. Based on this method, feeding network of the arrays becomes simple and compact and is easy to implement. And here the multiple optimization constrains include the number of elements, and the array aperture. Comparison of representative example is presented, and the results show that an enhancement of BCE and a depression of the sidelobe level outside of the receiving region (CSL) can be obtained through the proposed method.

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A fast and effective approach for simulating lossy nonuniform transmission line with the nonlinear terminations is presented. The method based on the improved delay extraction-based macromodeling algorithm (DEPACT) for the lossy uniform transmission line. Meanwhile, by reducing the approximation order, the macromodel is simplified and the simulation time is reduced. The simulation results are compared with the finite difference time domain (FDTD) method and good agreement is obtained.

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This paper presents a high power-efficient low voltage differential signaling (LVDS) output driver with adjustable feed-forward capacitor compensation. Compared to conventional LVDS output driver, the proposed output driver helps to significantly reduce the requirement of driving capability of pre-driver by increasing the rising and falling time of outputs. In addition, its output swing is adjustable based on different loadings. The proposed LVDS output driver consumes 3.04 mW with a transmission data rate of 6 Gb/s, achieving a power efficiency of 0.51 mW/Gb/s. This output driver circuit is implemented in a 65 nm CMOS process with a core area of 0.025 mm².

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A current noise reduction technique in chopper instrumentation amplifier (CIA) for high-impedance sensor is presented. The proposed technique is based on a time gating method to reduce time varying shot noise which is induced by channel charge injection of chopper switch transistors. An implemented CIA with the proposed time gating technique achieves more than 80-% noise reduction capability.

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