In this letter, the Chua’s circuit with an active variable memristor is presented for the first time. The central concept behind the variable memristor is that its memductance could be controlled by changing the cubic function which describes a relationship between the flux and charge of the memristor. It was found that chaotic dynamics of the variable-memristor-based Chua’s circuit could be easily controlled according to the memductance profile of the memristor. The controllable chaotic dynamics in the circuit were studied thoroughly by the numerical analysis. The rich dynamics of the Chua’s circuit using the proposed variable memristor were verified in terms of the time series, frequency spectra, phase states, bifurcation and Lyapunov exponents. These results were also confirmed by laboratory experiments.
A new method for extracting source/drain series resistances (Rsd) by combining split-CV and IV data of MOSFETs with multiple halo implant doses (called Multi-Dose Method) is proposed for the first time. This method eliminates the sensitivity of Rsd on effective channel length and considers halo-induced channel resistance increasing. Calibrated TCAD simulation and experimental data of 28-nm bulk MOSFETs with high-κ dielectric and metal gates are presented to support and validate the method. The maximum error of this method is within 5%, as compared with 63% for traditional methods. This method has been used as a monitor during technology optimization in foundry.
A time-domain (TD) asymptotic-numerical solution (TD-ANS) for a transient scattered field, which is a useful new reference solution on engineering applications, is developed for a two-dimensional transient scattered field from a cylindrically curved conducting open sheet excited by an ultra-wideband (UWB) pulse wave. The TD-ANS is represented by a combination of pulse wave elements; each element is obtained from a numerical integration. The TD-ANS is highly accurate and is useful in understanding transient scattering phenomena. The computation rate of the TD-ANS is very fast compared with that of a reference solution. The validity and usefulness of the proposed TD-ANS are confirmed by comparing with a reference solution and experimental-numerical results.
This paper presents a new method to reduce the standby leakage power consumption using the body bias and pin reordering technique for nanometer-scale CMOS circuits. The proposed method, unlike the conventional reverse body biasing (RBB) technique, considers gate leakage to minimize the negative effects of the existing RBB approach. This minimization of the negative effects can be achieved by intelligently applying proper body bias to the appropriate CMOS network based on its status (on-/off-state) with the aid of a pin reordering technique. Experimental results on ISCAS’85 benchmark circuits show that the proposed method can achieve improvements in terms of leakage power savings that range from 16% to 38% when compared with the previous works.
The use of a multiple-input floating-gate transistor as the main element for effecting the correlation of two binary sequences is proposed and validated. A complete architecture is proposed to implement a correlating system. The algorithm is discussed and the implementation of a circuit for 256-bit sequences in 0.35 µm CMOS technology is presented as a testing vehicle. Its use is furthermore proposed as a pilot baseband signal detector for a wireless communication system. The manufactured circuit offers favorable performance with a clock signal of up to 25 MHz with a 2.3 V supply voltage and 20 mW of power consumption.
We study the optical wavelength dependence of the Brillouin gain spectrum for a silica single-mode fiber in the range from 1511 to 1555 nm using a measurement setup containing an erbium-doped fiber amplifier (EDFA) in the Brillouin pump path. The Brillouin peak power and linewidth are clearly dependent on the pump wavelength, the trends of which correspond well with the wavelength dependence of the EDFA gain. This result suggests that we need to consider the unique wavelength dependence of the EDFA gain to practically obtain a higher Brillouin peak power and narrower linewidth at the telecommunication wavelength.
With the growing complexity of embedded VLSI products, traditional System-on-Chip (SoC) are facing severe challenges in the aspects of communicating speed and scalability. Network-on-Chip (NoC) has emerged as a viable alternative. In NoC design, application mapping is one of the most holistic researching dimensions, which maps the cores in the application to the routers in the NoC platform. Application mapping problem usually aims to reduce communication cost and power consumption of the overall system. In this paper, we focus on application mapping onto mesh network, and propose a novel two-phase heuristic algorithm. The first phase attempts to explore the potential searching spaces, while the second phase focuses on exploiting the local optima within the searching basin. To verify the effectiveness of the algorithm, this paper performs a quantitative comparisons between our proposed method and the existing mapping methods under both real application and custom generated application benchmarks.