Currently, low-cost spectrum devices are required in order to monitor the overall frequency bands for CR (Cognitive Radio) systems and EMF (Electromagnetic Field) strength measurement. This study was conducted to develop an FPGA (Field Programmable Gate Array) based spectrum sensor adopting switchable RBW (Resolution Bandwidth) with resolutions of 1 MHz and 100 kHz. In order to reduce the hardware complexity of the spectrum sensor, a shared multi-stage FIR filter architecture was utilized, which resulted in nearly a 90% cost reduction compared to those without the proposed architecture.

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In this paper, we have investigated bilayer HfN_x gate insulator utilizing ECR plasma sputtering especially for the electrical properties with metallic-phase HfN_0.5 gate electrode which was formed by in-situ process. After PMA of 500°C/10 min in N₂/4.9%H₂ ambient, the bilayer of HfN_1.3 (1.7 nm)/HfN_1.1 (0.9 nm) gate insulator formed on Si(100) showed the EOT of 0.61 nm, leakage current density (@V_FB −1 V) of 5.5 × 10⁻³ A/cm² and density of interface states (D_it) of 5.5 × 10¹¹ cm⁻² eV⁻¹. The n-MISFET with bilayer HfN_x gate insulator exhibited saturation mobility (μ_sat) of 47 cm²/(V s), which higher than the device with directly deposited HfN_1.3 gate insulator. HfN_x interfacial layer (IL) with low nitrogen concentration was found to significantly improve the interface properties of HfN_x gate stacks.

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Assuming two non-contiguous carriers, the impact of the power amplifier (PA) configuration is investigated. The mathematical derivations show that the minimum link performance (uplink data rate) occurs when the receive power allocation between carriers amounts to either 3 dB or −3 dB, depending on the bandwidth and path loss allocation. Moreover, it is shown that the link performance can be significantly improved by configuring the PA farther away from the worst-case operating points. The analysis matches well with the experimental results based on the PA measurement campaign.

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Typical electrical or piezoelectric force sensors may fail in the industrial applications with strong electromagnetic interference (EMI). To address this issue, this paper develops a new temperature-independent force transducer based on theories of elastic cantilever beam and Bragg wavelength shift in fiber Bragg gratings. The detailed design of the structure and theoretical analysis are given to introduce the measurement principle of the transducer and temperature compensation of fiber Bragg gratings (FBG). Extensive experiments have been conducted to evaluate the performance of the developed force transducer. Experimental results demonstrate that the developed FBG force transducer has a force sensitivity 84.43 pm/kN within a measured range from 0 to 50 kN, which is consistent with the theoretical sensitivity 87.77 pm/kN. Moreover, experimentally the transducer also achieves good linearity, repeatability and temperature independency. The developed force transducer can assist in monitoring the states of heavy-duty machines in the harsh industrial environment.

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A compact inline dual-band dual-mode bandpass filter (BPF) using single-layered substrate integrated waveguide (SIW) is implemented by etching an H-shaped slot on the top surface of two adjacent rectangular cavities. The H-shaped slot consisted of two coplanar waveguide (CPW) resonators and two SIW cavities can achieve two adjustable transmission poles at the upper and lower passbands, respectively. Good lower stopband performance is inherited from SIW. Two transmission zeros can be generated by the cross coupling through the resonators which are not in resonance to obtain high isolation between passbands and sharp skirt. To validate the concept, a dual-band filter is designed and fabricated, and good agreements are obtained between measured and simulated results.

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Precise voltage generation is a unique feature of superconducting single-flux-quantum (SFQ) circuits, and hence, several SFQ-based digital-to-analog converters (DACs) have been designed for metrological applications. In this letter, we propose a dual double-flux-quantum amplifier (dual-DFQA) that extends DAC output voltage from unipolar to bipolar. An SFQ-based DAC comprising a 4-bit variable pulse number multiplier and a ±20-fold dual-DFQA is fabricated using a niobium integration technology. A 1-kHz, ±0.29-mV sinusoidal voltage waveform is successfully synthesized.

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The Γ-point group velocity, v_gΓ, of lossy Dirac cone composite right/left-handed (CRLH) metamaterials is derived theoretically for the first time based on the equivalent circuit analysis. With the balanced CRLH condition, it is theoretically shown that v_gΓ takes the maximum value of a half of the speed of light in the background medium under the condition where the quality factors of the resonators in the series and shunt branches in the unit cell, Q_se and Q_sh, are equal, whereas under the condition of Q_se ≠ Q_sh, v_gΓ becomes smaller with the slow wave factor of κ = (k^1/2 + k^−1/2)⁻¹ where k is the quality factor ratio k = Q_sh/Q_se.

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A boosted replica cell voltage control scheme has been proposed for reducing the process-variation of SRAM sense amplifier. This technique suppresses the timing variation by boosting the replica cell voltage. Simulation result shows that the variation of the generated timing was 34.6% smaller when compared with conventional technique, and the cycle time is reduced by 17% at a 0.85 V VDD operation in TSMC 65 nm technology with this scheme.

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In this paper, attenuators with distributed resistor networks for attenuation up to 30 dB from DC to 25 GHz are presented. The distributed thin-film resistor network is embedded in coplanar waveguide (CPW) for microwave application. The sheet resistance and size of distributed thin-film resistor network are accurately calculated by conformal mapping and elliptic function for corresponding attenuation. The achieved attenuators is based on the use of tantalum-nitride (TaN) thin-film resistors with low mean temperature coefficient of resistance (TCR), high resistance silicon substrate and Au CPW. Microwave testing results show excellent performance with return losses better than 27 dB and insertion losses of 10.23 ± 0.12 dB, 15.23 ± 0.18 dB, 20.09 ± 0.23 dB and 29.17 ± 0.55 dB in the interesting frequency range.

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A simple nonlinear PFD circuit designed to achieve reduced reference spur and faster acquisition process for a PLL is proposed in this paper. The proposed nonlinear PFD is found to offer higher gain, eliminate glitches at the output and reduce both dead zone and reset delay when compared with the operation of conventional linear PFD (CL-PFD) and conventional NL-PFD (CNL-PFD). The PLL acquisition time got reduced by 50% and 11.69% while the reference spur 45% and 38.6% with respect to the CL-PFD and CNL-PFD respectively. Reference spur of −72.2 dBc, lock time of 1.548 µs, area of 0.2 mm² and power dissipation of 6.2 mW are obtained for the prototype PLL using Proposed NL-PFD designed with 180 nm CMOS process.

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This paper proposes a wide output range and tri-mode BUCK circuit which utilizes PWM mode, PFM mode and PSM mode at heavy, light and very light loads respectively. By shutting down the majority of the internal modules, employing minimum loop control and reducing the quiescent current, the design could lower the static power consumption. The work, therefore, could increase efficiency at very light load. The proposed BUCK is fabricated using SMIC 0.18 µm process. Test results show that when the input is 4 V and the output is 1.8 V, the efficiency of the proposed BUCK is 90% and 85% at 300 mA and 5 mA load current respectively.

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