In this paper, we propose a current mode linear CMOS temperature sensor profiting on increasing the accuracy of thermal monitoring. Concerning the temperature dependence of threshold voltage drift and mobility degradation, the proposed method removes the critical nonlinear terms realizing very linear relationship. Through driving two temperature-dependent current sources into particular operation region with different bias conditions, we utilize a compensation scheme among the resulted complementary temperature dependences of current sources which cancels major nonlinear effect. By TSMC 0.35µm CMOS process, within the temperature range from -20°C to 100°C, the measured results of an implemented chip show that temperature error and power consumption are ±0.15°C and 96µW respectively.
Mobile GPUs are used in modern portable devices to satisfy the growing requirements of 3D applications. These GPUs generally integrate hardware multithreaded shaders to improve the throughput for real-time rendering, but they depend on duplicate register files to maintain the context of each hardware thread. This work develops a demand-driven register file (DDRF) to reduce the power consumption by register files. The proposed DDRF is shared on demand among concurrent threads and turns off almost all unused registers. Experimental results reveal the DDRF uses 85.8% less power than a conventional multithreaded GPU. The chip area and circuit latency of DDRF are also discussed.
This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.
The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4nW at best case and 109.8nW at worst case, when AC signal and clock frequencies are 110MHz and 10MHz, respectively.
An integrated ultra stable current supply architecture for use in atomic resolution electron microscopy has been proposed, designed, and simulated. The system is designed to have an overall stability of .01ppm/°C, with similar stability for 20% changes in line voltage, and a drift in current of approximately 6×10-10min-1, all at 1A output current.
We investigated the changes in the electrical properties of a SiN/GaAs interface under high-temperature and high-humidity conditions, using photoreflectance (PR) spectroscopy and the electrical device characteristics. The PR spectra show the Franz-Keldysh oscillation (FKO); these spectra show that the period decreases after the sample is exposed to humidity. The electric field strength obtained from the FKO period indicates that the initial high electric field decreases with humidity exposure. Decomposed water molecules are supposed to diffuse into the SiN layer and react with the SiN/GaAs interface, causing a decrease in the interface states.
A simple, systematic and deterministic MATLAB simulation which employs Risbo method and analytical simulation is proposed to determine the optimal out-of-band gain to achieve a maximal SNR and the maximum stable amplitude in a multi-bit delta-sigma modulator. Using the proposed method, a 128MS/s, 2MHz signal bandwidth 4th order 2-bit continuous-time delta-sigma modulator is designed and implemented in 0.18µm CMOS technology to verify the concept. As a result, the modulator achieves a peak SNDR of 79.3dB and a dynamic range of 83dB for a 2MHz signal bandwidth (OSR = 32) while consuming only 7.8mW from 1.8V supply.
A novel coplanar waveguide (CPW) fed slot antenna for ultra-wideband (UWB) short range impulse radar systems is presented. A floating metal layer on the bottom of the antenna’s substrate is used to realize the one-sided directional radiation and high gain. The antenna’s dimensions are optimized to achieve impedance bandwidth of 7.8-9.2GHz. The final size of the antenna is 29mm × 16mm × 1.6mm. The proposed antenna is simulated, fabricated, and measured while a good agreement between the simulation and measurement results is obtained.
This paper describes the architecture of a divide-by-N prescaler and a divide-by-N/N+1 dual-modulus prescaler based on a shift register and a multi-input NOR gate. The divide-by-N prescaler has a circuit style similar to a linear feedback shift register (LFSR), except for the fact that a multi-input NOR gate is used instead of XOR gates. This architecture can be applied to various division ratios of N ≥ 2 by changing the numbers of flip-flops and NOR-gate inputs according to specific rules, which will be explained in this paper. The state of the prescaler runs through the correct loop without requiring a reset signal or an initialization circuit.
A novel high precision high order curvature-compensated bandgap reference (BGR) is presented in this paper designed using the subthreshold current of self-cascode transistors in standard digital 0.18µm CMOS process. Simultaneously its temperature coefficient is typically 4.6ppm/°C in the temperature range of -25 to 120°C with a supply current of 17.25µA. A power supply rejection ratio (PSRR) of -51dB is achieved while the layout area is no more than 0.0022mm2.