A novel dual-polarization edge-fed microstrip patch antenna was designed in this letter. In order to increase the isolation between the two ports with different polarizations and reduce the working modes affected by the feed line, two-section continuous current strips were separated from the metal ground plane. The measured result shows that the antenna has a port-to-port isolation better than 28.9dB from 5.725GHz to 5.875GHz, and particularly better than 32.6dB at 5.8GHz, which is improved more than 12dB compared with traditional antennas. Besides, a dual-polarization excitation can be realized within the single patch antenna for a single layer dielectric structure.

This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate receiver based on amplitude rectification. Compared with the conventional three-comparator structure, the PAM4 signal is converted into a 2-digit gray-code rather than a 3-digit thermometer-code. The amplitude is detected to decode the least significant bit (LSB), which allows the proposed receiver to use significantly less power by reducing the number of comparators. An inverter-based common-mode voltage stabilization circuit (CVSC) is proposed to reduce the effect of common-mode level changes as the amplitude is determined. To minimize the feedback delay, the 2-digit gray-code is fed back to DFE’s summer directly. By reducing the digit of the feedback signal, the power will be further reduced as the DFE tap increases. The device consumes 83.5 mW over a 55-nm process.

A power-efficient Single Event Upset (SEU)-tolerant pulse-triggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speed-insensitive and power-constrained applications.

This letter presents a 300GHz hybrid transceiver using CMOS and InP-HEMT, which achieves a maximum data rate of 56Gb/s. A 300GHz CMOS transceiver with a mixer-last transmitter mixer-first receiver is utilized to up- and down-convert the V-band IF signal to the 300GHz-band, while InP-HEMT is used for PA and LNA design. The transceiver also achieves wireless communication in ch.13-24 (1.76Gbaud), ch.39-44 (3.52Gbaud), ch.52-54 (7.04Gbaud) and ch.59 (10.56Gbaud) with lower than -16.7dB EVM. 64QAM modulation is also achieved for a 5Gbaud symbol rate. The CMOS transmitter and receiver consume 0.29W and 0.17W from a 1V supply, respectively, and the InP-HEMT PA and LNA consume 1.44W from a 1.2V supply.