This paper presents a vibrotactile belt to display precise directional information for visually impaired. Considering the characteristics of tactile perception, the torso-related transfer function was used to arrange actuators on the belt, and a coding algorithm using vibrotactile funneling illusion was proposed to display precise directional information. A psychophysical experiment was performed to evaluate the validity of the belt in displaying precise directional information. The experimental results indicated that the vibrotactile belt using our proposed coding algorithm achieves a resolution of 7.5 degrees with a high recognition accuracy of up to 91%. The current work provides valuable guidance for the design of vibrotactile navigation aids.
This paper presents a 15 W wireless power receiver, which integrates an improved full-wave synchronous rectifier. In order to improve the system efficiency, two auxiliary MOSFETs are proposed to balance the conduction losses and the switching losses, and a digital pulse width controller is proposed to compensate the turn off delay to prevent the reverse leakage current. The chip was fabricated with TSMC 0.18 µm 1 poly 5 metal BCD technology with an active area of 3.2 mm × 4.8 mm, and the measured performance of the system efficiency from the DC input of transmitter to the output of the receiver is achieved 88% at 12 V/1 A output.
This paper presents a novel 12T SRAM bitcell suitable for subthreshold operation. To make bit-interleaving structure feasible and eliminate half-select disturbance, the proposed cell features single pass-gate and dual pass-gates for read and write operation respectively. Additionally, the access path is decoupled by dedicate transistors from the true storage node, which both enhances the read stability and ensures enough sensing margin. Multi-threshold voltage metric is utilized to improve writability and leakage consumption. Simulation results show that the proposed cell offers 1.8X read static noise margin (RSNM) and 1.6X negative write static noise margin (WSNM) compared with traditional 6T cell at 0.4 V, sensing margin and access performance are improved compared with 10T cell.
High-speed digital-to-analog converter (DAC) is key component in instrument and automatic test equipment, radar and ultra-wideband (UWB) systems. In this paper, a two-channel 1.2 GSps, 8 bit RF DAC for Multi-Nyquist applications in 1 µm GaAs Technology is presented. Combining mode select circuit with synchronous latch simplifies design of the current source and layout of DAC core circuit. Measurement results demonstrate that the Differential Nonlinearity (DNL) is within ±0.15 LSB, and the Integral Nonlinearity (INL) is within ±0.4 LSB. For the normal mode, the Spurious Free Dynamic range (SFDR) is larger than 40 dB; for the mixing mode, output bandwidth is up to 1.8 GHz, and the SFDR is larger than 30 dB. Under a supply voltage of 5 Volts, the output swing is 1.1 Vpp, and the total power consumption is 1.7 Walts for both channels working.
Hardware implementation of LTE-Advanced systems using FPGA and ASIC technology is a highly promising technology. This article proposed a reliable and effective architecture for a LTE downlink transmitter under different antenna configurations including SISO 1×1; MIMO 2×2. The design has been synthesized using Altera Quartus II 13.1.4 on Altera Stratix-V 5SGSMD8K2F40I2. The parameter improving cost is introduced to evaluate the upgrading of resources caused by performance improvement. With this proposed structure, improving cost can be reduced compared with traditional method. The proposed plan is fabricated as an ASIC using SMIC 55-nm CMOS technology. Finally, the design is demonstrated in the test platform, showing a successful performance.
A 1–30 GHz ultra-wideband low noise amplifier (LNA) MMIC with a simplified on-chip temperature-compensation circuit is presented in this paper. The temperature-compensation circuit composed of two GaAs mesa resistors and two Nickel Chromium (Ni/Cr) thin-film resistors is able to compensate the variation of temperature accurately over a wide operating frequency range. The fabricated LNA has demonstrated the improvement of gain variation from 3.4 to 0.8 dB (0.4 dB/Stage) in the temperature range from −55 °C to +125 °C. It exhibits the lowest the gain variation (0.0022 dB/°C/Stage) with temperature ever reported for the ultra-wideband LNA. By contrasting the LNA with and without the temperature-compensation circuit, it is also found that the use of the temperature-compensation circuit neither degrades other aspects of the circuit performance nor increases the area of the original amplifier chip.
In this paper, the hardware design of frequent items counter is proposed. The key idea is to create a matrix of binary-value by using an array of binary-decoder to decode all of the input items in parallel. After that, an array of population-count modules are applied to the rows of the matrix to generate counting results. The architecture was implemented with five options of bit/item from 6-bit/item to 10-bit/item, and seven options of count-register bit-width from 8-bit counters to 32-bit counters. Therefore, there were 35 different versions of implementation presented in this paper. Those implementations were built on the Field-Programmable Gate Array (FPGA) board of Altera Arria V SoC development kit. Also, they were synthesized to chips with the process technology of 65 nm Silicon On Thin Buried-Oxide (SOTB). The experimental results of the proposed architecture achieved outstanding timing performances compared to other attempts to date.
An inductive power supply with concentric coreless transformer is proposed for the ultrasonic transducer on machine tools. The concentric coreless transformer is designed not to increase mounting weight onto the spindle and transfer power to the ultrasonic transducer without contact losses. A switching power supply composed of a series-parallel resonant compensation circuit and a full-bridge inverter is also designed to convert the power from stationary side to the rotary ultrasonic transducer (UST) through the coreless concentric transformer. A primary-side controller based on fed back primary-side current is also proposed for output voltage control. Therefore, there are only the secondary winding and the parallel compensation capacitor required to be mounted on to the spindle. From the experimental results, it can be seen that the proposed power supply can provide a stable AC power with 25 kHz/70 V to the ultrasonic transducer. The efficiency of the proposed power supply is up to 90% and the efficiency difference between stationary and rotary operations is only about 2%.