IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 6
Showing 1-13 articles out of 13 articles from the selected issue
LETTER
  • Jea-Shik Shin, Insang Song, Moon-Chul Lee, Chul-Soo Kim, Sang Uk Son, ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20130938
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 06, 2014
    JOURNALS FREE ACCESS
    A bulk acoustic wave (BAW) resonator with suppressed energy loss is proposed. Implemented with air edge reflector and current spreading electrode along the perimeter region of the BAW, the resonator successfully suppresses the acoustic wave leakage and the electric energy loss as well. As results of optimized lateral structure, the Q-factor at anti-resonance frequency (Qa) is significantly improved to over 2100. Furthermore, the peak insertion loss exhibits as low as 0.04dB and effective electro-mechanical coupling coefficient (kt2), which is essential to achieve wide band-width of RF filters, is 6.54%.
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  • Yoshinao Mizugaki, Haruna Takahashi, Hiroshi Shimada
    Type: LETTER
    Subject area: Superconducting electronics
    2014 Volume 11 Issue 6 Pages 20140054
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: February 28, 2014
    JOURNALS FREE ACCESS
    We demonstrate a zero-crossing Shapiro step generated in a magnetically-coupled Josephson gate, where a long Josephson junction and a control line are placed in-line. The operation is based on the imbalanced evolution of the junction phases owing to the different amplitudes of the positive and negative critical current. A test circuit was fabricated using a Nb/AlOx/Nb junction technology. When we applied a rf signal of 15.2GHz, we observed a Shapiro step that crossed the zero-current axis at the voltage position of the 1st order. The experimental results were quantitatively reproduced by simulation.
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  • Chunwei Zhang, Siyang Liu, Daying Sun, Chaohui Yu, Weifeng Sun
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20140055
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 05, 2014
    JOURNALS FREE ACCESS
    A novel lateral double diffused MOSFET (LDMOS) structure with partial buried-oxide layer under the n-drift region, which is suitable for the bulk silicon epitaxial process, is proposed. The introduction of the buried-oxide layer produces an inversion layer at buried-oxide/p-sub interface and achieves better reduced surface field (RESURF) effect comparing with the conventional device with buried-pwell. Moreover, the buried-oxide can prevent the impurity diffusion and improve the doping concentration of the n-drift region. As a result, the proposed structure improves the breakdown voltage about 12% and increases the current capability over 30% at the same time.
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  • Jun Luo, Qijun Huang, Sheng Chang, Hao Wang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20140056
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 06, 2014
    JOURNALS FREE ACCESS
    This paper presents an efficient reconstruction method in block compressed imaging (BCI) for natural images. To avoid the high complexity and give a time-efficient approach, block-based separable two-dimension (2D) linear reconstruction method is proposed. The techniques of adaptive sampling (AS) and separable reconstruction are combined to yield a competitive solution for BCI. The AS is utilized by employing more measurements in the texture redundant blocks. The separable 2D reconstruction uses linear approach based on minimum mean square error (MMSE) to reduce the decoder complexity. Experiment results demonstrate that the proposed scheme can efficiently reduce the reconstruction complexity and give a competitive image quality compared to non-linear approaches.
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  • Zonglin Liu, Sheng Ma, Yang Guo
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 6 Pages 20140078
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: February 28, 2014
    JOURNALS FREE ACCESS
    The floating-point multiplication is one of the most basic and frequent digital signal processing operations, and its accuracy and throughput greatly decide the overall accuracy and throughput of the digital signal processors. Based on vectorizing a conventional double precision multiplier, we propose a multiple precision floating-point multiplier. It supports either one double precision multiplication for high accuracy or two parallel single precision multiplications for high throughput. The evaluation results show that the proposed multiplier is suitable for embedded DSPs. It consumes 8.9% less area than two single precision multipliers. Compared the configuration with a single precision multiplier and a double precision multiplier, the proposed multiplier consumes 30.1% less area.
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  • Taewoo Han, Inhyuk Choi, Sungho Kang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 6 Pages 20140093
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 06, 2014
    JOURNALS FREE ACCESS
    The increased usages of multi-core systems diminish per-core complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.
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  • G. Kavya, V. ThulasiBai
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 6 Pages 20140097
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 03, 2014
    JOURNALS FREE ACCESS
    A lot of care must be taken to choose the processor for the biomedical application to meet out the real time constrains. Also the complexity of the programming increases with the multi processing environments. The real time Operating systems can support the problem up to a particular limit based on the processor architecture. When the hard real time parameters needs higher Multi processing environment, the processor struck to a limit. This paper deals with the wearable telemonitoring and Lab on chip feature for the 12 lead ECG interpretation and analysis with maintaining the patient history in case of arrhythmia like diseases. Instead of implementing the application on a single processor or FPGA solution, it is implemented using NIOS II (Altera IP core) based multi core architecture. The System on chip consists of GPS tracking, GSM base band work and the ECG processing elements and this proposes a most user friendly and wearable single medical chip. The idea of this paper is to improve the efficiency and speed of processing of the ECG interpretation and telemonitoring by separating tasks between the processors.
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  • Hyun-Seok Lee, Hyun-Gyu Park, Hyo-Tae Kim, Kyung-Tae Kim
    Type: LETTER
    Subject area: Electromagnetic theory
    2014 Volume 11 Issue 6 Pages 20140102
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 05, 2014
    JOURNALS FREE ACCESS
    High-frequency predictions of radar cross-sections are usually performed using the well-known shooting and bouncing rays (SBR) method. SBR needs many incident ray tubes for accurate results. Therefore, its computation time is proportional to the square of the number of ray tubes, often resulting in a prohibitively large computation time, especially for electrically large and complex objects. To address this problem, a new ray tube merging scheme called line tracing SBR (LT-SBR) is proposed to reduce the number of incident rays. Simulation results reveal that the LT-SBR has a computational advantage over the conventional SBR and recently introduced beam tracing SBR.
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  • S. Vijayakumar, Reeba Korah
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 6 Pages 20140109
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 05, 2014
    JOURNALS FREE ACCESS
    Scaling the feature size under 0.1 micron leads to the domination of leakage power along with the consumption by interconnects also. Among alternatives for power optimization, the circuit level approach is the best option for low power consumption which is used in this work to incorporate a novel MOS Switch Integrated Ultra-Low Power (MOSSI-ULP) 1-bit full adder using 32nm BPTM file. It is then used as a base cell in an array multiplier. Its performance is compared with similar kind of adders like SERF, ULPFA, TGA, TFA and BBL-PT. The analysis shows that the proposed design consumes a maximum of 11 time lower average power than ULPFA. Though MOSSI-ULP switches with a moderate frequency, it requires 17 times less PDP than ULPFA and maximum of 3 times less area.
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  • Hyo-jong Kim, Donghwan Seo, Byung-geun Lee
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 6 Pages 20140132
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    Settling behavior of the binary-weighted switched-capacitor digital-to-analog converter output is analyzed and a design method for fast settling is presented. A calibration circuit that effectively reduces settling time beyond the process limit is also proposed and verified with various simulations.
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  • Takaaki Ibuchi, Tsuyoshi Funaki
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20140142
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 06, 2014
    JOURNALS FREE ACCESS
    Active power-factor correction (PFC) circuits are commonly used in the first stage of single-phase AC/DC power converters to improve the power factor and low-order harmonic distortion. In continuous current mode (CCM) PFC circuits, the reverse recovery current of a PN diode is induced during its turn-off following the turn-on operation of a MOSFET, which causes not only a switching loss but also a switching noise in the PFC circuit. This study investigates the loss and conducted noise characteristics of a PFC circuit by comparing the difference among silicon PiN diodes, silicon Schottky barrier diodes (SBDs), and silicon carbide SBDs.
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  • Byunggyu Yu
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20140143
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    Islanding phenomenon of Photovoltaic (PV) system should be prevented because it causes a safety problem to utility service personnel and power supply facilities. Until now, various anti-islanding methods have been proposed. However, these are mostly focus on the islanding prevention method for single PV system. Recently, PV system using micro-inverters are widely disseminated in the field. Accordingly, an islanding issue for multiple PV micro-inverter systems has been paid attention due to their interaction not to detect islanding, even though the single micro-inverter unit can prevent islanding when the single unit is only tested. This paper presents an improved active frequency drift (AFD) anti-islanding method for multiple PV micro-inverter systems. The proposed method injects every half-line cycle asymmetrical signals and uses the correlation between the injected asymmetrical signal and the corresponding half line cycle. The proposed method is verified by using PSIM simulation, compared with the conventional AFD method. It shows that the proposed method is highly effective to detect islanding even under multiple micro-inverter system while the conventional one doesn't detect islanding.
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  • Mansoor Ali Khan, Hyun Chang Park
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 6 Pages 20140163
    Published: March 25, 2014
    Released: March 25, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    In this paper, an effective T-gate with Drain-Field-Plate (TGDFP) technology is used in GaN-based HEMT for high breakdown voltage of 500V and drain current of 540mA/mm. Silvaco TCAD simulation showed that normally-off TGDFP HEMT with recessed gate length of 0.5µm exhibited high threshold voltage up to +1V and transconductance of 140mS/mm along with frequency operation in S-band (∼3GHz). The proposed lateral TGDFP HEMT provides desirable features for both Power and RF applications.
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