This paper presents a 1200V-class reverse conducting insulated gate bipolar transistor (RC-IGBT) with low switching energy consumption (LE-RC-IGBT). Its structure was designed in accordance with the latest enhanced trench and field stop technology while incorporating an anti-parallel Free Wheeling Diode (FWD) between the adjacent FS-IGBT cells. With the Emitter Shorted Diode (ESD) technology employed in the design of the FWD structure, the FWD and FS-IGBT can be made simultaneously. By using the same trench etching technique of the gate process, oxide trench was formed on the back side of the device to increase the short-circuit resistance between the N+ Collector and the P+ Collector on the back of the RC-IGBT. The voltage snapback phenomenon of the conventional RC-IGBT was completely eliminated. The electrical characteristics of the RC-IGBT were investigated by using Sentaurus-TCAD. Simulation results show that the switching energy consumption of the proposed LE-RC-IGBT is reduced by approximately 50%compared with the conventional one.
Compared with the traditional two-stage boost inverter, the quasi-Z-source inverter can achieve boost under the condition of direct current, and the single-stage structure can achieve two-stage functions, so it can improve the reliability and transmission efficiency of the photovoltaic system. This paper studies the nonlinear dynamic behavior of single-phase photovoltaic quasi-Z-source inverter under unipolar SPWM modulation. Firstly, according to the working principle of quasi-Z-source inverter, the state equations of the system are derived. Based on the state equations, the accurate discrete iterative mapping model of quasi-Z-source inverter is established. Then, the nonlinear dynamic behavior of single-phase quasi-Z-source inverter under different proportional coefficients is analyzed from the perspectives of folding diagram, bifurcation diagram and folding phase diagram. The time-domain waveform obtained on the Matlab/Simulink simulation platform verifies the correctness of the theoretical analysis. Finally, the waveforms and conclusions obtained by the experiment are consistent with the waveforms and conclusions obtained by the simulation. Therefore, this study has certain theoretical significance for deeply understanding the working stability of single-phase photovoltaic quasi-Z-source inverter, and also has certain practical engineering value, which provides a theoretical basis for the design of the main circuit and control circuit of the system.
This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.
This paper presents a novel first-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To decrease dynamic power consumption, one-side switching instead (OSSI) method and higher-bit switching instead (HBSI) method are adopted in our proposed noise-shaping architecture. Dynamic SAR logic and dynamic comparator are used to further reduce power consumption. In addition, a low supply voltage is applied to this ADC, which can decrease static current leakage. The proposed noise-shaping SAR ADC was fabricated in 0.18um 1P4M CMOS technology, which occupies an active area of 0.185mm2. The prototype chip consumes 89nW at 25kHz sampling rate. The measurement shows 58.2dB signal to noise and distortion ratio (SNDR) can be achieved.
This letter presents a 28-38GHz low-noise-amplifier (LNA) monolithic microwave integrated circuit (MMIC) using 0.15µm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. Inductive degeneration and shunt-series peaking techniques are employed to obtain simultaneous input and noise matching (SINM) and wideband flat gain. A novel wideband multistage noise matching technique based on a high-pass matching network is proposed to achieve low NF and further improve gain flatness over a wide frequency range. A four-stage LNA prototype is designed and fabricated based on the proposed technique. Measurement results show that the proposed LNA has a 1.6-dB minimum NF and an average gain of 23.7dB in the entire operating band. S11 and S22 are better than -10dB from 30 to 37GHz. The measured output 1-dB compression point (OP1dB) is higher than 14.8dBm from 28 to 38GHz. The chip is realized within 2.1*1.5mm2 and consumes 56mA current from a 5V supply.
Recently, a very interesting behavior of crosstalk (XT) between diagonal cores (diagonal XT) in a square-layout uncoupled four-core fiber (UC-4CF) that grows quadratically with fiber length has been reported. In this paper, the behavior of intercore XT in square-layout UC-4CFs is investigated on the basis of a coupled-power theory. To make it easy to understand the physical mechanism of intercore XT behavior, we derive an approximate solution of coupled-power equations. We show that there exists a range of fiber lengths within which the diagonal XT grows quadratically. Finally, we propose a heterogeneous square-layout UC-4CF in which intercore XT could be further suppressed.