This paper proposes an automatic threshold converged CMOS optical receiver employing a threshold convergence technique to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. A threshold concentrator is introduced at the receiver, in order to improve digital audio quality by aligning various logic thresholds of the input signals into a constant one. Simulation results demonstrate that the designed optical receiver in a 0.18-µm CMOS technology can successfully reduce pulse width distortion within -2% and circuit complexity.
We describe a high speed adder that employs a carry-lookahead structure and uses low-voltage-swing pass-transistor-based Manchester carry chain. This structure is implemented in 65nm technology and accommodates 15GHz clock frequency at the slowest corner which is 20% higher than the highest speed in the previously studied high-speed structures.
This paper describes a high-speed CMOS track-and-hold (T/H) circuit with low distortion. We propose a T/H circuit with a body-bias control circuit to reduce distortion. This control circuit maintains a constant body bias for a switching MOS transistor in tracking mode. This reduces the variation in the threshold voltage due to the body-bias effect, thereby resulting in low distortion. The test chip fabricated using 90-nm CMOS technology shows a high SFDR of 56.3dB at a sampling frequency of 1GHz.
Using chaotic signals, we evaluate the performance of the EASI(Equivariant Adaptive Separation via Independence) algorithm, which is a basic algorithm among various on-line ICA (Independent Component Analysis) algorithms. We found that the EASI algorithm in fixed-point (16-bit) arithmetic can recover the chaotic signals successfully as well as the algorithm in floating-point arithmetic. We can implement the algorithm in fixed-point arithmetic to Virtex-IV SX25 FPGA (Field Programmable Gate Arrays) up to the 4x4 design.