IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 5
Showing 1-16 articles out of 16 articles from the selected issue
LETTER
  • R. Fernández-García, I. Gil
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20120864
    Published: March 01, 2013
    Released: March 01, 2013
    JOURNALS FREE ACCESS
    It is accepted that the electromagnetic interference should be addressed with statistical analysis. Usually the impact of electromagnetic interference on different electronic samples is evaluated and the average immunity level is used as a reference. However, this method does not provide enough information to know the probability of failure to the electromagnetic interferences of an electronic circuit. An alternative statistical analysis based on the Weibull distribution is presented. The typical and proposed methods have been compared in order to analyse the electromagnetic immunity performance of two types of operational amplifier. The results confirm the feasibility of the proposed method.
    Download PDF (443K)
  • Hamza M. R. Al-Khafaji, S. A. Aljunid, Angela Amphawan, Hilal A. Fadhi ...
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130044
    Published: March 04, 2013
    Released: March 04, 2013
    JOURNALS FREE ACCESS
    To boost the performance of spectral-amplitude coding optical code-division multiple-access (SAC-OCDMA) systems, the need for an effective solution to diminish phase-induced intensity noise (PIIN) is becoming progressively more crucial. In this letter, two PIIN suppression approaches: semiconductor optical amplifier (SOA)-based noise cleaning, and single photodiode detection (SPD) are employed. The performance of the hybrid SOA/SPD scheme is validated through simulation experiments. Our results show that SOA/SPD scheme remarkably improves the performance and increases the throughput of SAC-OCDMA system.
    Download PDF (594K)
  • Xuan Zhu, Chunqing Wu, Yuhua Tang, Junjie Wu, Xun Yi
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130013
    Published: March 05, 2013
    Released: March 05, 2013
    JOURNALS FREE ACCESS
    Utilizing memristor to obtain multi-level memory in nano-crossbar is a promising approach to enhance the memory density. In this paper, we proposed a solution for multi-level programming of memristor in nanocrossbar, which can be implemented on nanocrossbar without the need for extra selective devices. Meanwhile, using a general device model, this solution is demonstrated to be adaptive to a wide range of memristors that have been experimentally fabricated through HSPICE simulation.
    Download PDF (477K)
  • Kaichen Zhang, Wei Li, Ning Li, Junyan Ren
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130016
    Published: March 05, 2013
    Released: March 05, 2013
    JOURNALS FREE ACCESS
    A 0.1-12GHz Low Noise Amplifier (LNA) with an active balun is proposed for multi-standard applications. In order to realize wideband matching and single-to-differential (S2D) conversion simultaneously, a single-end resistive negative feedback amplifier is adopted as the first stage for input impedance matching, and a novel active balun consisting of common source amplifier and source follower is designed as latter stage for S2D conversion. This LNA is fabricated in a 0.13-µm CMOS process with an active area of 0.33mm2. The measurement results show that over the full band of interest, the LNA achieves a minimum noise figure (NF) of 3.2dB, input reflection coefficient S11 less than -9.3dB, a power gain (S21) of 14.1dB and -3.6dBm IIP3 with a power consumption of 10.8mW from 1.2-V supply.
    Download PDF (876K)
  • Shuang He, Peng Gao, Ling Xiong, Wanting Zhou, Liang Xu
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130020
    Published: March 05, 2013
    Released: March 05, 2013
    JOURNALS FREE ACCESS
    A novel planar antenna with WiMAX and WLAN band-notched characteristics is presented for ultra-wideband (UWB) applications. The UWB antenna consists of a staircase-shaped radiating element, a microstrip feedline and a modified ground plane. To realize WiMAX band-notched characteristic, a pair of hook-shaped slots is etched on the radiating element. Two folded stubs extending from the ground plane are used to reject the WLAN band for the first time. The antenna meets a bandwidth from 2.95 to 11.6GHz, with two notched-bands of 3.25-3.95GHz (WiMAX) and 5.00-6.50GHz (WLAN), respectively. Measured and simulated results of the impedance bandwidth, gain, and radiation patterns are presented and discussed.
    Download PDF (720K)
  • Teruo Suzuki, Kenji Shiraishi
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130029
    Published: March 05, 2013
    Released: March 05, 2013
    JOURNALS FREE ACCESS
    The degree of leaning of the Electro-Static Discharge (ESD) wave form (hereinafter referred as RON) of ESD protection parameters is closely related to the internal core circuit damage. Accurate measurement of RON requires stable short calibration with Transmission Line Pulse (TLP). In particular, for the high-precision ESD design of the thin gate oxide transistor in the most advanced technology, the high accuracy RON measurement of TLP is required. During short calibration, we found the contact resistance between the packaged sample and integrated circuit (IC) socket varied depending on the calibration current. Scanning Electron Microscope (SEM) analysis of contacts made it clear.
    Download PDF (826K)
  • Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Kee-Won Kwon
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20120902
    Published: March 06, 2013
    Released: March 06, 2013
    JOURNALS FREE ACCESS
    This paper presents a divider-less all-digital PLL (ADPLL) with supply insensitivity. We employ a feed-forward inverter to make the oscillator insensitive to supply variation and utilize the delta-sigma modulation to improve the resolution. The on-chip calibration tracks the optimum compensation strength for process and nominal voltage variations. We use an asynchronous counter to decide the phase error for low power. The proposed ADPLL was fabricated in a 0.13µm CMOS process. The silicon area of the ADPLL is 0.26mm2 and the power consumption is 5.8mW at 320MHz. The spur level with the proposed compensation scheme was improved from −57dBc to −84dBc with an intentional supply noise.
    Download PDF (2611K)
  • Hui Dong Lee, Jaeho Jung, Kwangchun Lee
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130038
    Published: March 06, 2013
    Released: March 06, 2013
    JOURNALS FREE ACCESS
    A LC-VCO topology without a varactor device has been proposed. The oscillator includes a variable capacitance block for a frequency tuning. The block consists of two transistors and two capacitors. The LC-VCO has been fabricated in a 130-nm CMOS technology. The measured results show operation frequencies of 3.73GHz to 3.94GHz and a phase noise of −119.1dBc/Hz at 1-MHz offset frequency. Power consumption is 5.9mA from a 1.2V supply.
    Download PDF (560K)
  • Keiji Goto, Le Hoang Loc
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130100
    Published: March 06, 2013
    Released: March 06, 2013
    JOURNALS FREE ACCESS
    We derive the novel asymptotic solutions for the scattered field when a cylindrical wave is incident on a coated conducting cylinder with a thin lossy dielectric material. We show that the extended UTD (uniform geometrical theory of diffraction) solution and the modified UTD solution derived by retaining the second order term are uniformly applicable in the transition region near the shadow boundary and in the deep shadow region in which the conventional UTD shadow region solution produces the substantial errors. The validity of the asymptotic solutions proposed here is confirmed by comparing with the exact solution.
    Download PDF (809K)
  • Oguzhan Kizilbey, Osman Palamutçuogullari, Siddik Binboga Yarma ...
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130104
    Published: March 06, 2013
    Released: March 06, 2013
    JOURNALS FREE ACCESS
    In this study, balanced and single ended class-E power amplifiers (PAs) were designed and realized for 3.5-3.8GHz band by using Gallium Nitride high electron mobility transistor (GaN HEMT). Realizations were made on low loss Rogers RT5880 dielectric material which has 0.254mm thickness and 2.2 dielectric constant. Proposed balanced class-E PA has approximately 20W (43dBm) output power with 80% peak power added efficiency (PAE) and shows a very favorable combination of output power, PAE and suppressed even order harmonics compared to the single ended class-E PA prototype.
    Download PDF (901K)
  • In Jun Park, Changhwan Shin
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130108
    Published: March 06, 2013
    Released: March 06, 2013
    JOURNALS FREE ACCESS
    Quasi-planar tri-gate (QPT) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated by a low-power 28-nm complementary metal-oxide-semiconductor (CMOS) technology, in order to investigate the effect of double-patterning and double-etching (2P2E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (VTH) variation. We experimentally verified that the LER profile obtained by the 2P2E 193nm immersion photolithography technique has a relatively lower spatial frequency (i.e., longer correlation length) than that obtained by the conventional (i.e., single-patterning and single-etching, or 1P1E) photolithography technique, although they have a comparable root-mean-square deviation and fractal dimension. Using Monte Carlo (MC) simulations to analyze the random VTH variations in the QPT bulk MOSFETs, we confirmed that the 2P2E-LER-induced VTH variation is much smaller than the total VTH variation in the 28nm QPT CMOS technology.
    Download PDF (301K)
  • S. M. Shamsul Alam, GoangSeog Choi
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20120878
    Published: March 07, 2013
    Released: March 07, 2013
    JOURNALS FREE ACCESS
    This paper reports the result of a comparison between reduced instruction set computing and the transport triggered architecture. Because of the simplicity and efficiency of the transport triggered architecture, its processor requires less execution cycles compared to the OpenRisc processor. This paper also presents a case study about designing an Architecture Definition File for a transport triggered architecture-based design tool, and it depicts how the Architecture Definition File structures are responsible for implementing high-speed design. In a custom Architecture Definition File, a new function unit is designed to improve processor performance, and it shows that the cycle count required to implement the Cyclic Redundancy Check algorithm drops to 7 executions from 5031.
    Download PDF (965K)
  • Koichi Narahara
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20120963
    Published: March 08, 2013
    Released: March 08, 2013
    JOURNALS FREE ACCESS
    We investigate left-handed (LH) travelling-wave field-effect transistors (TWFETs) to observe the reverse Doppler effect. Due to the nonlinearity, a TWFET can support shock fronts that can reflect incoming waves. By introducing the composite right/left-handed line structure to a TWFET, it enables to support LH waves. Because the shock front functions as a moving reflection wall to the incoming LH waves, we can expect the reverse Doppler effect to cause in an LH TWFET. After explaining the structure and fundamental properties, we report the reverse Doppler effect observed experimentally in the devise.
    Download PDF (1278K)
  • Hua Fan, Qi Wei, Fei Qiao, Huazhong Yang
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130047
    Published: March 14, 2013
    Released: March 14, 2013
    JOURNALS FREE ACCESS
    This paper presents a 12-bit 100MS/s time-interleaved successive approximation register (SAR) ADC designed for intermediate frequency 3G receivers. The 12-bit 100MS/s 2-channel ADC with voltage-controlled delay lines (VCDLs) based time-domain comparator is designed in 65nm CMOS, single-channel 12-bit 50MS/s pipelined SAR ADC consists of a 6-bit MDAC first stage and a 7-bit SAR ADC second stage, the operational amplifier is shared between the two channels for low power dissipation. A novel redundant SAR ADC used in the first stage is proposed to avoid comparator offset issue. Moreover, tri-level flash-SAR ADC is proposed and used in the second stage, the total unit capacitors to realize a 7-bit tri-level flash-SAR ADC are 50% of the conventional two’s complement flash-SAR architecture. Simulation results in 65nm CMOS process show that, the 12-bit 100MS/s ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 73.32dB (11.89 ENOB), a spurious free dynamic range (SFDR) of 90.65dB with a 2.7MHz input tone, while dissipating 10mW from a 1.2V supply.
    Download PDF (1408K)
  • Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130081
    Published: March 14, 2013
    Released: March 14, 2013
    JOURNALS FREE ACCESS
    This paper studies performance and timing failure probability of time-shifted redundant circuits and path-/circuit-replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for the path-replica and circuit-replica, the false negative error probability of the circuit-replica is approximately two orders of magnitude less than that of the path-replica circuits. When attaining a false negative error of zero, the probability of error detection and re-execution in time-shifted redundant circuits is comparable to, or rather smaller than that of the path-replica circuits.
    Download PDF (1055K)
  • Youngil Kim, Sangsun Lee
    Type: LETTER
    2013 Volume 10 Issue 5 Pages 20130127
    Published: March 14, 2013
    Released: March 14, 2013
    JOURNALS FREE ACCESS
    This letter proposes area-efficient peripheral circuit techniques for 3D Solid State Drive (SSD) with NAND flash memories. We reduced charge pump stage using external high voltage of 12V and 5V, and improve target voltage accuracy using a cascode error amplifier of high voltage linear regulator. Also, we proposed fast transient response active mode VDC using NMOS pass element with external high voltage of 5V.
    Download PDF (1794K)
feedback
Top