This paper presents a serial multi-channel front-end readout ASIC with a novel architecture and timing control scheme, for the application of flat-panel X-ray, linear detectors and other similar fields. The proposed architecture features the single multi-range selectable integrator, two multiplexed correlated double sampling (CDS) circuits, and the differential buffer output. With the proposed sequential timing control, each channel can output data to the corresponding CDS circuit with no delay when the integration state is ended. So, the channel circuit is simplified. In addition, the proposed architecture and timing control scheme enables the readout ASICs to be cascaded for more channels with tunable conversion rates. To verify the proposed architecture and timing control scheme, a 32-channel readout ASIC was fabricated in TSMC 250nm mixed CMOS signal process. The die size is 2.8 × 2mm². At room temperature, the measured equivalent input noise (EIN) is 25ppm of full-scale value (FSR) with an integration range of 12pC. The measured integral non-linearity is less than 0.04%, and the average power consumption is 2mW per channel. When four ASICs are cascaded, 128 channels are achieved, and a conversion rate over than 30kS/s is measured.

In this paper, current mode logic based on the three-independent-gate field effect transistor (TIGFET) is introduced as the circuit-level side-channel attack (SCA) countermeasures, and a SCA-resilience flip-flop (DyCML) is designed to make the power consumption constant. Then, a simplified advanced encryption system (AES) is built, and power analysis is performed to evaluate the SCA-resistance efficacy. Simulation results show that the key with the TIGFET-based DyCML is not revealed with 255 power traces. The proposed design occupies less area usage and requires less delay overhead compared to the original TIGFET-based true single-phase clock (TSPC) and modified TSPC (mTSPC).

As the latest touch-based input equipment of consumer electronics, touch screen is a convenient and natural human-machine interaction vehicle. However, it has not separated from the scope of “interactive input”. Tactile display adds the tactile output along with the interactive input and helps the operator to perceive tactile feedback of texture, profile, etc., which increases the immersion of the operator significantly. In this study, a friction-varying texture tactile display which is composed of resonance module, positioning module and vision display module was designed by using the squeeze film effect. In this device, a piece of 194 × 100 × 2 mm transparent glass was used as the touch tablet, which can provide a large working area and is easy to be integrated with common consumer electronics. The feasibility and precision of the designed friction-varying tactile display in simulation of texture were further verified by a psychophysical experiment.

This work presents a 32-bit Reduced Instruction Set Computer fifth-generation (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) accelerator. The accelerator is implemented inside the core and being used by the software via custom instruction. The used microprocessor is the VexRiscv with the Instruction Set Architecture (ISA) of RV32IM; that means 32-bit RISC-V including Integer and Multiplication. The experimental results were collected using Field-Programmable Gate Array (FPGA) on the DE2-115 development kit and Application Specific Integrated Chip (ASIC) synthesizer on 180-nm CMOS process library.

This paper presents an ultra-low power 32.768 kHz crystal oscillator circuit for the real-time clock (RTC) generation. A negative feedback amplitude control loop is employed to reduce the oscillation amplitude and the energy loss of the crystal. To further reduce power consumption, the inverting amplifier is powered on periodically by a duty-cycling control pulse, which reduces the static power of the amplifier significantly. Trading off among power consumption, area and design complexity for generating a precise duty cycle pulse, the output square wave of the crystal oscillator circuit is used as the control pulse. The circuit is designed in 55-nm CMOS process with an area of 0.04mm². It shows a power consumption of 8.83nW which cuts the power consumption by 37% comparing with the circuit without pulse control. The proposed circuit achieves a great temperature stability of 0.14ppm/℃ from -40℃ to 100℃ and a power supply sensitivity of 30.5ppm/V over supply voltage of 0.5-0.8V.