A modified floating biased common-gate transimpedance amplifier with improved low corner frequency is introduced. It is also shown that gm-boosting technique can be utilized for differential implementation of this transimpedance amplifier, without degrading the circuit sensitivity or using any off-chip components. HSPICE simulations for differential implementation illustrate more than two orders of magnitudes improvement of low corner frequency, about 80% increase in gain, and 20% reduction in input referred noise, compared to those of conventional single-ended floating biased common gate transimpedance amplifier.
In this paper, we propose a new optical alignment system using Hadamard transformation that is designed for aligning multiple channel optical components. A conventional optical alignment system assumes that the whole channels of the components are perfectly aligned with two detectors, which are placed at the end of the outermost channels of the components, indicate the maximum optical power. The proposed system is able to give us the optical power information of each channel with using one detector. The proposed optical alignment system can make up for the drawback of the conventional optical alignment system.
Routing congestion is one of the main factors in designing in deep submicron technology that may cause unroutability of the design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the physical design flow in order to improve the congestion of the design. Experimental results show that for the attempted benchmarks, the overflow congestion was reduced by up to 40.03% without any degradation in clock frequency and negligible power consumption overhead.
Capacitance between terminals of a power semiconductor device substantially affects on its switching operation. This paper presents a capacitance-voltage (C-V) characterization system for measuring high voltage SiC-JFET and the results. The C-V characterization system enables one to impose high drain-source voltage to the device and extracts the capacitance between two of three terminals in FET by eliminating its influence on the neighboring terminal. The capacitance between the gate and drain, and the drain and source represents the hybrid structure of the lateral channel and vertical drift layer of the SiC-JFET.
Zero-IF architecture has become popular for WLAN receivers due to its simplicity. However, zero-IF receivers suffer from the effect of IQ imbalance and carrier frequency offset which may have huge impacts on their performance. Several joint compensation schemes for these influences have been researched, based on the correlation between adjacent channel frequency responses. However, by the limitation assuming the perfect symbol synchronization, these schemes show performance degradation when a symbol timing error exists. In this paper, we analyze the effect of symbol timing errors and propose a robust and efficient compensation scheme. Simulation results show the proposed algorithm achieves an SNR gain of 7.3dB over the conventional algorithm when a symbol timing error occurs.
Progress in LTPS TFT technology enabled the system-on-panel to prevail in small FPDs. And high speed TFT circuit technique is essential for expanding the system-on-panel applications. In this work, all p-channel, LTPS TFT, current mode inverter/buffer is introduced. To overcome the power hungry nature of the current mode circuit, small logic swing, complementary input, and systematic design method have been developed. The design method is essential tool to obtain the best trade off between power and delay. It is proved that the CML inverter/buffer can be designed to consume less power and to operate at higher speed than CMOS inverter.