With scaling technology node, increasing Multi-Cell Upsets (MCU) is dramatically challenging the reliable system design. Network on Chip (NoC) as the communication infrastructure in a many-core processor, is also suffering the serious MCU impacts. Therefore, a place-aware redundancy methodology is proposed to alleviate the MCU impacts on NoC via exploiting MCU correlation. The simulation results demonstrate that, compared with 50% error recovery of latest works, the proposed approach achieves up to 95.8% error recovery with even only 6.91% extra area cost.
Eye tracking, or detecting where the user is looking at, is expected as a new type of user interfaces, with including the phenomenon of rapid eye movement, so called saccade. However, real-time tracking of saccade is difficult with the conventional image processing systems for their long processing time and latency against the speed of saccade. In this paper, we describe the design of the CMOS image sensor for eye tracking with high speed and low latency capability, as well as its evaluation results.
A 30–43 GHz cascode sub-harmonic mixer is presented using 0.13-µm CMOS process. This mixer comprises cascode RF amplifier stage, sub-harmonic mixer core and IF low pass filter. By utilizing cascode structure and LO-gate pumped mixer transistor, a novel bias condition with negative gate-source voltage and zero drain-source voltage is proposed. This mixer achieves resistive sub-harmonic mixing as well as alleviates the contradiction between conversion loss and port isolation of single FET mixer. This sub-harmonic mixer achieves conversion loss of 5.8–10 dB with LO power of 6 dBm and 2LO-to-RF isolation better than 36 dB during 30–43 GHz. The measured intermediated frequency 3 dB-bandwidth is from 30 MHz to 5 GHz and the input 1 dB compression point is −9 dBm.
A novel waveguide directional filter with compact-size and low insertion loss is proposed in this letter. The basic structure consists of a pair of rectangular waveguides placed parallel to each other along their narrow side and two identical band-pass filters connect them via two coupling slots. For easy of fabrication and assembling, all the band-pass filters and waveguides have a uniform height, that is all the components of the directional filter are in a single-layer waveguide. It is easy machining by standard computer numerical controlled (CNC) techniques to match the requirement for low cost. For verification purpose, an X-band single-layer waveguide directional filter has been manufactured and measured. The measured results show a insertion loss better than 0.1 dB, a return loss lower than −17.5 dB and a isolation better than −22.5 dB, good band-pass and band-elimination responses are also obtained over the frequency range from 7.25 GHz to 9.75 GHz. The good agreement has been found between the simulated and measured results.
High-frequency isolation quasi-Z-source inverter is extensively used in photovoltaic power generation systems due to its high step-up voltage ratio, high conversion efficiency, and electrical isolation. However, this type of inverter is likely to cause bifurcation and chaos in the system due to improper selection of parameters or external interference and the strong nonlinear characteristics of the inverter. The accurate discrete iterative mapping model of the Z-source inverter is developed to optimize the system parameters and improve its stability. The nonlinear phenomena of high-frequency isolated quasi-Z-source inverter are analyzed by using bifurcation diagram and folded graph methods, and the stable operation areas of the system are determined by a new method of coefficient linearization. Experiments were performed to validate the accuracy of the theoretical analysis. This paper provides a reference for the quasi-Z-source inverter isolation to maintain stable operation under high-frequency conditions and serves as a theoretical basis for further optimization design and system control.
This paper presents a modified feed-forward (FF) delta-sigma modulator architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. By eliminating the internal FF path from the first integrator output, the number of capacitors in the analog adder is reduced and the load capacitance of the first integrator becomes independent of the quantizer resolution. To verify the proposed modulator architecture, a three-bit second-order delta-sigma analog-to-digital converter (ADC) is implemented. The prototype ADC is fabricated in a 0.18 µm CMOS process with an active die area of 0.095 mm2. It achieves a dynamic range (DR) of 101.0 dB and a peak signal-to-noise and distortion ratio (SNDR) of 97.1 dB in a 2 kHz signal bandwidth while consuming 63.4 µW from a 1.8 V/1.65 V power supply.
In this letter, a low input boost converter with continuous conduction mode is presented for energy harvesting application. The maximum power point tracking (MPPT) efficiency at low input voltage is improved by using the proposed input-ripple control technique. Fabricated in a 0.35 µm CMOS process, the boost converter generates an output voltage of 3 V from the input voltage as low as 25 mV. The measurement results show that the boost converter achieves an MPPT efficiency of 91% at 25-mV input and a peak power conversion efficiency of 82.7% at 250-mV input.
This paper proposes a high performance physical unclonable function (PUF) implemented in a standard 65 nm CMOS process. The PUF cell is derived from SRAM-PUF cell, but it only use the NMOS or PMOS cross coupling structure with two additional access transistors. Random process variations between two cross coupling transistors are digitized to produce one bit output. Post-layout simulation results show that the 2k-bit PUF has high randomness and uniqueness, and it has some excellent features: (1) small PUF cell with a minimum feature size of 240F2; (2) high energy efficiency of 17.3 fJ/b at nominal 1.2 V; (3) excellent stability: only 2.6% bit-error-rate (BER) across a wide temperature range (−40–100 °C) and 10% VDD variations.
This work studied the electrical characteristics of silicon-on-insulator (SOI) multi-stacked nanowire junctionless FET (NW-JL-FET) and SOI hybrid junctionless FinFET (H-JL-FET) using TCAD simulation. The scalability of the above two structures was investigated by simulating device performance with gate lengths from 30 nm to 5 nm. Results show that NW-JL-FET has better performance than that of H-JL-FET due to gate all around structure. However, H-JL-FET still has good performance under ultra-small gate length indicating FinFET still could be a competitor for 5 nm and beyond technique nodes.
The auxiliary diagnosis and debugging of filters play an increasingly important role in the design of microwave filters. In particular, aggressive space mapping (ASM) is one of the most commonly used debugging methods. This paper introduces ASM and designs a seventh-order microstrip interdigital filter with a center frequency of 24 GHz and a fractional bandwidth of 25% with ASM. The filter reached design indexes after four iterations, which greatly reduces the number of simulations in fine model, thereby saving time. It was fabricated on high resistance silicon substrate and the size of the chip is 6.8 mm × 2.4 mm × 0.4 mm. The measurement results show that the fabricated filter has a center frequency of 24 GHz, a fractional bandwidth of 24.17%, an insertion loss of 1.95 dB, a return loss of 12 dB, and an out-of-band rejection of 40 dB.