A built-in method of on-chip solar battery in a CMOS LSI is proposed. The proposed solar battery can be formed using conventional CMOS process technology. It can generate a high voltage of 0.6-0.83V by a series connection structure of two types of p-n junction diodes formed with the CMOS circuit simultaneously on the LSI chip. The generated voltage is sufficient to drive the conventional CMOS circuit without modification. The test chip was produced experimentally using conventional 0.35µm CMOS technology, and the drive performance of the on-chip solar battery was evaluated. The conversion efficiency of the proposed solar battery was 2.6%. The area of the solar battery required for power consumption was 6.1mm2/µW in the case of the 2000lx illumination.
A method of designing compact multiple-input combinational logic circuits is proposed. We show that i) fundamental logic gates can be constructed by a small number of collision-based fusion gates, ii) multiple-input logic gates are constructed in a systematic manner, iii) the number of transistors in specific logic gates constructed by the proposed method is significantly smaller than that of conventional logic gates.
H.264 video coding standard supports 3D video through dedicated Stereo Video Information (SVI) Supplemental Enhancement Information (SEI) message. This SEI message allows main and auxiliary frames be coded into alternative pictures in which disparity information can also be utilized. However, due to the presence of both disparity and motion vectors at the neighborhood of a given macroblock, the H.264 predicted motion vector motion vector concept becomes less efficient. This paper presents a novel motion and disparity vector prediction algorithm that overcomes this drawback. Results show that the proposed algorithm achieves up to 1dB gain compared to the conventional motion vector prediction algorithm.
The simplified adiabatic SRAM is proposed which enables gradual charging during writing mode so that problems of electromigration and hot carrier effects can be resolved. For simplicity, we do not use a regenerator circuit for charge recycling in the circuit. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that we set the memory cell power line to be in a high-impedance state. Then, we input adiabatic signal from one bit line to charge the memory cell power line to VDD. This writing method enables gradual discharging and charging. As for reading, the word line voltage is decreased to Vth, or it is changed stepwise while the voltages of bit lines are verified. These reading methods enable the gradual change. With the gradual charge transfer in writing and reading modes, the SRAM can avoid electromigration and hot-carrier effects even in the less-than-45-nm process, while it maintains an operating voltage of 1V or more.
We report two-step-recess gate InP HEMTs with a new process option suitable for producing a wide recess. In the new devices the gate recess is completely covered with a passivation film. Though the gate recess is extremely wide, a transconductance of 1S/mm and a cutoff frequency of 208GHz are achieved with 100-nm gate devices. Moreover, a huge improvement in the drain reliability is achieved by the wide recess which reduces hot-carrier-induced degradation, and by the full passivation which eliminates the instability related to the recess surface.
In this paper, we reported the effective mobility and the interface-state density of La2O3 nMISFETs fabricated under different post deposition annealing (PDA) conditions; annealing temperature (300°C - 600°C) and ambient (N2 or O2). High effective mobility of 312cm2/Vs and low interface-state density of 6 × 1010cm-2/eV were obtained from La2O3 nMISFET with equivalent oxide thickness (EOT) of 1.7nm after PDA at 300°C in N2 ambient for 10 minutes. Gate leakage current density was 6.8 × 10-6A/cm2. We found that peak effective mobility decreased with increasing anneal temperature, regardless of annealing ambient. We also observed a monotonous relationship between effective mobility and interface-state density. This behavior suggests that lowering the interface-state density is essential to obtain high mobility in the high-κ/Si structure.
Turbo code is recommended as a channel coding scheme, which has been shown to be capable of performing close to the Shannon Limit. In this paper, we compare the performance of both convolutional and block turbo codes over AWGN and Rayleigh fading channels. It is observed that the performance of convolutional turbo code is slightly better in the water fall region and the coding gain ranges from 0.5 to 0.7dB at BER of 10-4 depending on the channel conditions. But below BER of 10-4 or 10-5 an error floor occurs in the case of convolutional turbo code. Block turbo codes tend to outperform convolutional turbo codes for low BER.
This paper describes magnetic sensor array characteristics of MOS Hall-plates and the comparison with split-drain MAGFETs. A problem of the magnetic sensor array is the offset deviation which is caused by process imperfection. To investigate the magnetic sensor array characteristics suitable for an array structure, a test chip integrating magnetic sensor arrays with different structures of MOS Hall-plates and split-drain MAGFETs are fabricated using 0.25µm standard CMOS process. The ratio of the sensor signal to offset deviation of the MOS Hall-plates is three times higher than that of the split-drain MAGFET. From the measurement results of MOS Hall-plates with different shapes, it is found that a Hall-plate with longer channel and probes located closer to the center of the channel has small offset deviation.