To improve the steady-state performance of the dual three-phase permanent magnet synchronous motor with high torque ripple and high harmonic current, this paper proposes a hybrid voltage vector model predictive current control algorithm (MPCC). Firstly, based on the virtual voltage vectors synthesized using the vector characteristics of the fundamental and harmonic subspaces, hybrid voltage vectors are synthesized from the virtual voltage vectors and the zero vector to increase the voltage vector amplitude range to reduce torque ripple and to suppress harmonic currents. Then a vector selection method is proposed to reduce the number of alternative vectors and the calculation burden of the MPCC. Finally, the realization of corresponding PWM modulation is given. The simulation results show that the method effectively suppresses harmonic currents and torque ripple and increases the steady-state performance of the motor.
Based on the study of the electric double layer interface changes and the influence of the geomagnetic field during the underwater motion of the towed antenna, the formation mechanism of the motion polarization noise and motion-induced noise caused by the antenna motion is explained, and the corresponding relationship between the motion noise and the motion acceleration of the towed antenna is analyzed. Experiments are designed and verified. The results show that the movement of the towed antenna in the conductive medium will increase the low-frequency noise level of the antenna, which is mainly concentrated below 300Hz, and the noise floor increases more obviously with the increase of the movement rate. In addition, the low-frequency noise introduced by the antenna motion is controlled by the motion fluctuation frequency, and the noise frequency is the same as the motion acceleration frequency, which is consistent with the theoretical analysis.
This work presents a transformer matching X band MMIC power amplifier (PA) on gallium nitride (GaN) process. A port impedance modeling-based transformer design method is proposed and analyzed. The method simplifies the transformer matching network design process, improves matching impedance accuracy, and relieves designer’s burden. A novel compact temperature compensation (TC) circuit is also used in this design. The PA design on the 0.25µm MMIC GaN technology process, and occupies 1.594mm2 area. At a 28V supply, the gain and output power of PA reaches 15dB and 29dBm respectively. Additionally, the designed TC circuit stabilizes PA current consumption from temperature variation. From -55 to 85°C, the PA current consumption stability improves by more than 60% by using the proposed TC bias circuit.
The paper studies a unit cell mismatch scrambling method for a high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) for communication applications. This can be implemented with relatively simple interconnections and scrambling circuits, compared to that based on the 2-dimentional (2D) layout.
This paper presents a 21.3-24.5Gb/s phase locked loop (PLL)-based reference-less clock and data recovery (CDR) circuit. A cascode-coupled technique is used in the design of the quadrature voltage-controlled oscillator (VCO), which eliminates the phenomenon of dual-mode oscillation, provides a stable phase sequence for frequency acquisition and ensures the correct loop locking. The dual loop topology is adopted to realize a wide frequency acquisition range and an autonomous transition from frequency locking to phase locking, while the PLL-based structure brings in an excellent jitter performance. When the data rate of the input PRBS9 is 24.5Gb/s, the measured peak-to-peak jitter and the root-mean-square (RMS) jitter of the recovered clock are 2.7ps and 0.39ps respectively, and the peak-to-peak jitter and the RMS jitter of the recovered data are 7.7ps and 1.5ps respectively. Implemented in 55-nm CMOS technology, the CDR circuit occupies a core area of 0.7mm2 and consumes 170mW at 1.2V power supply.
Inspired by the idea of memristor designed in standard CMOS process and based on TSMC 0.18µm CMOS process, an analytical model describing memristive characteristics was presented. Then an adaptive image recognition hardware neural network consisting of input neuron, CMOS-based memristor array and operation and feedback neurons, was proposed and was implemented using analog circuit. The synaptic weights are adaptivevly modified according to input image signal. The simulation results indicated that our image recognition circuit overcame the bottleneck of conventional von Neumann computing architecture, and successfully completed the training and recognizing for letter images of z, v and n without the assistance of digital circuit and software. Our proposed CMOS memristor and adaptive image recognition circuit have great application in the field of image recognition due to its good compatibility with standard CMOS technology.
With the increasing requirements for charging speed of portable electronic products and the demand for portable performance, the fast-charging adapter industry is facing challenges. Adapters mainly have the problems of being too large in volume, low power density and low charging efficiency. This paper introduces an ultra-density adaptor for type-c power delivery (PD) applications. The principle of active clamp flyback converter (ACF) is explained briefly. Advanced technology with Gallium nitride (GaN) devices and novel ACF controller are applied. Power density is increased by current mirror integration method. It can achieve high efficiency, especially at low line input. Finally, a 28.4cc 65W prototype based on GaN Power IC and ACF controller was made with EMI CE passing. The efficiency at full load reaches about 93% with current mirror integration method.
In 3-D charge trap (CT) NAND flash memory, program/erase (P/E) cycling tests are performed, and the degradation of cell characteristics is investigated. The mechanism of mid-gap voltage (Vmg) shift difference between erased state and programmed state is presented and it is verified by technology computer-aided design (TCAD) simulation configured identically to the real device. TCAD simulation also makes it possible to extract the trap density through the current fitting. Generation of interface traps (Nit) and bulk traps in the tunneling oxide (Not) has the form of a power-law of the number of P/E cycles. Furthermore, it is experimentally found that the degradation of cell characteristics is mainly caused by hole tunneling current from the poly-silicon channel during erase operation.
Pitch and yaw angular speed measurements are vitally important parameters for monitoring the condition of precision machines. In this letter, we propose a dynamic pitch and yaw angular speed measurement system based on line scan vision. The characteristic line scan image can be considered a discrete time sequence, and each column of pixels represents a different time. A double light-spot centroid and double Gaussian fitting algorithm are developed to obtain the centroid coordinates. Kalman data fusion is employed to enhance the accuracy of the obtained measurement results. The experimental results prove that the proposed method is effective and highly accuracy.