Predictive direct power control (PDPC) and sliding mode control (SMC) have been proposed as effective schemes for three-phase rectifiers. However, the conventional PDPC still has sampling power errors caused by control delay. Furthermore, the existing SMC can not well work with PDPC to provide fast error convergence and strong robustness during both start-up and load step change periods. To solve the problems above, this paper proposes an improved hybrid SMC-PDPC control scheme for Vienna rectifier, which uses lagrangian liner interpolation to predict the next sampling power value with eliminating inner-loop power errors. Additionally, this paper presents a novel SMC based on squared voltage in the outer loop. Experimental results based on 10 kW prototype circuit are presented to confirm the effectiveness of the proposed scheme.
In this study, we present a significantly enhanced signal detection method using harmonic frequency in a lock-in amplifier (LIA). This method reduces the effect of flicker noise that limits the signal-to-noise ratio in a conventional DC-based LIA. Furthermore, it has a definite advantage that it is not necessary to match the phase between the input and the reference signals. To verify such merits, we constructed a hybrid LIA circuit and conducted experiments. The results demonstrated that the dynamic range improved by approximately 43 dB compared to a conventional DC-based LIA. Moreover, the harmonic LIA output is successfully obtained regardless of the phase difference.
A radiation-hardened 64-Kb Programmable Read Only Memory (PROM) fabricated by 0.18 um commercial technology is proposed. The Radiation-Harden-By-Design (RHBD) technique is applied in the design of the PROM. At the cell level, memory cells consisting of two high reliable antifuse elements are used. At the circuit level, robust sense amplifiers are designed with Dual Interlocked Cell (DICE) latches added to the radiation sensitive nodes. Furthermore, the enclosed NMOS and guard rings are applied at the layout level. As the measurement showed, the PROM could operate at the temperature between −55 and +125°C with 55 ns maximum address access time. The TID (Total Ionizing Dose) test showed that irradiation dose to 5M rad(Si) negligibly impacted standby current and access time. In the heavy ion test, no SEU (Single Event Upset) and no SEL (Single Event Latch-up) were observed up to LET (Linear Energy Transfer) of 64.4 Mev·cm2/mg.
In this paper, a switching satellite antenna array capable of realizing high gain coverage in half space is designed, and a multi-antenna system conforming to the structure of the pedestal is combined with a feed based on RF switch. In the feed network, 19 beams were designed for spatial coverage, so that an antenna pattern of right-hand circular polarization gain of not less than 8 dB within azimuth angle 0–360° and pitch angle 0–70° was achieved. The area ratio of circular polarization is less than 3 dB. The test results are in good agreement with the simulation results.
Nowadays most FPGAs use SRAM-based technology, which are sensitive to radiation-induced Single Event Upsets (SEUs). To validate the reliability of FPGA, fault injection is widely used to simulate the SEUs. However, current fault injection researches mostly focus on offline. With the emerging of dynamic partial reconfiguration (DPR) technology, the requirement of online fault injection is becoming more and more urgent. This paper proposed an ICAP controller-based online fault injection method and developed an ICAP controller for DPR system. The designed ICAP controller injects SEUs by firstly reading back one frame from the specific address to local RAM, and then reconfiguring the fault frame to the original position. Moreover, it consumes half resources used by the Xilinx’ AXI_HWICAP, a quarter of those used by AC_ICAP and one tenth of those used by FT_ICAP. The experiments were conducted on a Xilinx Artix7 and validated the effectiveness of the proposed method.
Charging mobile electronic devices is a hot topic in the field of wireless power transfer. The change of mutual inductance during the movement of the electronic device will cause the output voltage to fluctuate and the power transfer efficiency to drop. In order to solve these problems, this paper proposes a CLC compensation network that is embedded between the power supply and each transmitter coil. Optimizing the parameters of the CLC compensation networks can ensure that the position-varying load obtains stable voltage while ensuring high power transfer efficiency. Specific theoretical analysis of output voltage control and power transmission efficiency optimization is detailed in the article. Finally, a typical experimental platform is established and the result of the experiment can verify the theory.
In this paper, an optically controlled phased array antenna with two elements is introduced. The phases of RF signal generated by an optical beat note are controlled by the beat note frequency. The tilting of the beam pattern from an array antenna is achieved.
Traditional Doherty power amplifiers (DPAs) have severely limited bandwidth due to the presence of a quarter wavelength (λ/4) compensation microwave line. This paper proposes a novel phase compensation and impedance transform structure that can maintain a 90-degree phase shift over a wide frequency range, which is a good alternative to traditional λ/4 microwave line. To verify the validity of the proposed structure, a DPA has been designed and fabricated based on the proposed structure. The saturated output power reaches 43 dBm, and the output efficiency of the drain stage is more than 65% from 2.6 GHz to 3.8 GHz. Meanwhile, over 43% drain efficiency is obtained at 6 dB back-off power.
With the CMOS technology scaling down, the normal latch is more susceptible to soft errors caused by radiation particles. In this paper, we proposed a low-power and highly reliable radiation hardened latch to enhance the single event upset (SEU) tolerance. Based on DICE latch and Muller C-element circuit, the proposed latch can provide 100% fault tolerance, which can be used for space applications in severe ray radiation environments. The simulation show that’s it not only can completely tolerate an SEU on any one of its internal single node, but it also can provide double-node and triple-node upsets protection for facultative initial state of the latch. What’s more, compared with other hardened latches, the proposed cell has comparable or better performance in the matter of delay time and power.
When the NAND Flash memory is used beyond specific retention time, data stored in NAND Flash memory may not be read out correctly due to retention error. In this paper, a word line interference (WI) based data recovery technique is proposed to recover retention-failed data. By using WI, a large amount of electrons can be re-injected into retention-failed cells with one program operation. To improve recovery efficiency and recover retention error in a block, an iterated WI recovery algorithm which combines WI and previously reported DRRP technique is proposed. Experiment results show that WI recovery technique gains a higher recovery efficiency compared with DRRP technique.
This letter describes the design and realization of the low-cost power amplifier module with operation frequency at 7.9–8.4 GHz. Realized power amplifier module employing fully internally matched GaN HEMT power amplifier exhibits 10 W output power and associated gain of 50.1 dB at X-band frequency for satellite communications. The module exhibits the 20% of power added efficiency (PAE), whereas the main power amplifier with internally matched HEMT device achieves 29.3% of PAE. 3rd order intermodulation level is less than −35 dBc with 7 dB output power back-off condition. Proposed housing method of the power amplifier module reduces the thermal distribution by more than 30°C.
Non-circular multi-core fibers (NC-MCFs) to accommodate more than 100 cores per fiber are proposed for super-dense space-division multiplexing. The proposed MCFs have the potential for easier splicing/connection and their applicability to highly-dense ribbon MCFs for ultra-high capacity optical transport systems.
A multi-layer stacking scheme using a sol-gel SiO2 fabrication technique was developed towards stacking thick layers of >0.8 µm for cladding and passivation layers of optical waveguides. The multi-layer stacking scheme, which improves the intrinsic stress problem especially in case of thick layer stacking, enables a >0.8 µm sol-gel SiO2 thickness without cracking and peeling issues. As a result, thick layer of 3.5 µm with high surface resistivity of >6.6 × 1013 Ω/m was obtained. Furthermore, a-Si/SiO2 waveguide (cladding thickness: 1.9 µm) was realized to confirm the fundamental potential as a cladding layer.
System-on-Chip (SoC) design using hardware Intellectual Property (IP) cores has become an integral part and pervasive practice in industries to realize error-free complex devices. However, IP vendors face major challenges in protecting hardware IPs against hardware Trojans and preventing revenue loss due to IP piracy. Obfuscation is an exact solution for protecting hardware IP against various attacks such as piracy, overbuilding and tampering. Logic locking technique allows locking outputs by fixed logic values and generates invalid output of the function if a wrong unlocking key was applied. In this paper, a novel technique called configurable Gate Diffusion Input (GDI) based logic obfuscation is proposed to enhance the security of hardware IPs. Configurable GDI based obfuscated cell inserts extra gates in the logic path of the circuit with minimum overheads to secure an IC from piracy and overbuilding. The proposed technique is simulated and synthesized using Synopsys software tool. Simulation results on ISCAS–89 benchmark circuits show that high levels of security are achieved through a well formulated obfuscation scheme at less than 10% area, power and delay overheads.
This paper proposes a harmonic controlled symmetric Doherty power amplifier (DPA) for large back-off applications. For efficiency enhancement, the harmonic impedances of the carrier and peaking amplifiers are controlled in the continuous class-F mode. To extend the back-off range, unlike the traditional DPA, the output impedance of the peaking amplifier locates far away from infinity at the edge of the Smith chart, which can further improve the efficiency of the carrier amplifier. For verification, a 3.3–3.8 GHz symmetric DPA was designed and measured. The designed DPA can deliver an efficiency of 45%–48% at 9 dB back-off power over the whole frequency band with a maximum output power larger than 44 dBm. When driven by a 40-MHz modulated signal, the DPA exhibits an adjacent channel leakage ratio of better than –50 dBc after linearization at an average output power of 36.5 dBm.