A monolithic 12-bit digitally calibrated digital-to-analog converter (DAC) has been developed. The principle of proportional match design in the resistor switch network, its structural characteristics and the resistor network for calibration are presented. A close-loop calibration circuit with differential difference amplifier (DDA) has been proposed to eliminate the variation of switch resistance caused by temperature and supply-voltage. Moreover, this paper also presents the proposed automatic calibration algorithm based on fuse trim, which can reduce the number of times to trim the resistors and simplify the trimming process. The proposed self-calibrated and digitally trimmed DAC has been fabricated with a 0.5µm bipolar-CMOS-DMOS (BCDMOS) process. Measurement results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) of the developed DAC after calibration achieve -0.65LSB～+0.6LSB and -0.6LSB～+0.25LSB, respectively. The settling time of the developed DAC achieves 1µs.
An isosceles right triangular Substrate integrated waveguide cavity is presented. By etching the modified complementary compact microstrip resonant cell on the metal upper surface of isosceles right triangular SIW cavity, different bandpass filters are realized by using different feed ports. The triangular SIW bandpass filter with two right-angle sides as feed ports is designed and implemented. The center frequency is 17.8 GHz, the fractional bandwidth is 36.52%, the in-band insertion loss is less than 0.3 dB, and the in-band return loss is better than -20 dB. The existence of two transmission zeros in stopband significantly improves selectivity of the filter.
A broadband cross dipole antenna for ultra-high frequency (UHF) near-field radio frequency identification (RFID) applications is proposed in this paper. The proposed antenna with two perpendicular coplanar dipoles can identify the tags that placed random perpendicularly to the antenna’s surface. A prototype is fabricated and tested for verification. By adjusting the length of one dipole, the broadband characteristic is obtained. Measured results show that the operating bandwidth (S11<-10dB) is about 210MHz from 852 to 1062MHz. Meanwhile, a strong and uniform magnetic-field distribution surrounding the antenna is achieved with an interrogation zone of 142mm×142mm.
A novel time-domain (TD) asymptotic-numerical solution (novel TD-ANS) is proposed for a backward transient scattered magnetic field when an ultra-wideband (UWB) pulse wave is incident on a coated metal cylinder which is made of a metal cylinder covered with a homogeneous medium layer. The TD-ANS is expressed by two kinds of notations. First is represented by a combination of a direct geometric optical ray (DGO) and a reflected GO (RGO). Second is given by a combination of a DGO and a RGO series. The TD-ANS is useful in understanding backward transient electromagnetic wave scattering because it can reproduce the wave packet of a reflected wave by superposing multiple RGO components. The accuracy and validity of the TD-ANS are confirmed by comparing with a reference solution.
For internet-of-things (IoT) terminals, which consist of many sensors and beacons, wiring and using battery are ineffective power supply methods due to excessive installation and maintenance work cost. Nowadays, existing wireless power transmission technologies are still immature. In this paper, LED-array optical wireless power transmission (OWPT) systems which have a portable size and can supply electricity power of nearly 400 mW remotely at 1 m for compact IoT terminals are designed and demonstrated.
This letter presents a narrowband third-order waveguide bandpass filter (BPF) with extended out-of-band response. The filter is composed of three offset resonators, and each resonator is constructed by shifting half of a rectangular resonator, featuring a very large distance between the first and second resonant frequencies. The BPF was designed with a center frequency (f0) of 9.5 GHz and a passband bandwidth of 100 MHz and was fabricated by using the Computer Numerical Control (CNC) milling process. The experiment results show that the BPF has an average insertion loss of 0.45 dB, a return loss of >16 dB, and a 30-dB stopband suppression up to 1.75 f0. The measured results agree well with the electromagnetic (EM) simulations.
An advanced motor driving circuit based on digital sampling load and adaptive segment control of power MOSFET to realize improved transfer efficiency is presented in this paper. A digital block is employed to detect the duty cycle of PWM signal which indirectly reflects the load condition. According to the duty cycle of PWM signal, a digital segment controller is employed to perform adaptively scaling the area of the power MOSFET to ensure current capacity of the power MOSFET just meets the load requirements. The power MOSFET is divided into three segments according to area ratio of 1:2:4. Area scaling step is 1/7 of the whole power MOSFET. The adaptive segmented controller contains duty cycle detector and segment controller is implemented based on FPGA. The correctness and feasibility of the proposed method are verified by experiments of a DC motor driver.
In next-generation wireless communication, photonic control of a remote array antenna is an attractive technique because it enables both low-loss transmission and high-speed beam forming in the base station. In this paper, we propose a novel remote phase control method with a small phase drift for array antenna driving in a fiber-wireless system. Our idea is based on the combination of two intensity-modulated optical waves at different wavelengths with a constant modulation phase difference, which is produced using wavelength dispersion in the transmission line. The useful features of the proposed method for remote driving of an array antenna are experimentally demonstrated.
Area-Energy efficient CORDICs are presented. The proposed CORDICs adopt a new Elementary-Angle-Set, based on which the elementary angle composition of input angle can be directly determined without angle recoding, and the Angle-Set ensures the directions of vector micro-rotation are deterministic anti-clockwise in first quadrant. Based on the Angle-Set, elements sin and cos of rotation matrices are expanded into exponential expressions with base-2, which are convenient to circuit implementation. To improve calculation accuracy, initial values of rotation vectors are added with fixed offsets to pre-compensate the scaling-free expansions errors. Implemented in multiple FPGA devices and CMOS processes, the CORDICs achieve the lowest resource consumption, the least number of stages and the best energy-efficiency compared with other state-of-the-art works.
Many approaches have been presented to broaden the impedance bandwidths of low profile dielectric resonator antennas (DRAs). However, few of them can achieve a balanced behaviour in terms of bandwidth, gain, radiation patterns, antenna size, etc. In this paper, a low profile wideband probe-fed DRA is proposed. By centrally placing a probe-fed strip DR in a 2×2 parasitic DR lattice, balanced antenna performance can be achieved. A DRA prototype was fabricated and tested for demonstration. Measured results show that the antenna can achieve an impedance bandwidth of 24%, a peak gain of 7.92 dBi with a compact DR size of 0.47×0.47×0.07λ03 (λ0 is the wavelength of the center frequency). Besides, symmetrical and consistent radiation patterns can be maintained within the band.
With the continuous drive toward integrated circuits (ICs) scaling, more test patterns are required in testing. However, the large number of patterns continues to increase test time and test costs. Thus, test costs of ICs are becoming more crucial yet more challenging. In this paper, we propose a novel adaptive test strategy to reduce test costs without increasing test escape, and using shortest path first (SPF) algorithm combined with K-Nearest Neighbor (KNN) to reorder the test patterns. The patterns which identify faults earlier are moved forward and applied first so as to save test time. In addition, the optimal test patterns are searched by means of a polynomial regression function and it provides a trade-off between test cost and test escape. Consequently, the optimization problem is converted into a mathematical function, in order to achieve broader applicability and generality. Experimental results demonstrate that the proposed method achieved 54.2 seconds time savings but leads to almost negligible test escapes increasing compared with traditional methods. The test pattern reordering method aims to find defects as early as possible. Furthermore, the proposed algorithm is completely software based and incurs no additional hardware overhead.