In this letter, we propose a low-latency semi-systolic architecture for multiplication based on the shifted polynomial basis over finite fields. The proposed multiplier saves at least 49.9% time complexity and 23.7% area-time complexity as compared to the related multipliers. The proposed multiplier can be used as a core circuit for various applications.

A fourth-order high-pass filter is proposed, which is formed by spiral inductors and TSV capacitors. The components of this filter rely on the TSV technology, which is generally regarded as vertical interconnection but now used to compose capacitor. The comparison of the results between finite element method and equivalent electric circuit obviously proves that they have nearly equal filtering characteristics including cut-off frequency and roll-drop rate. Moreover, the comparisons are made among the HPFs based on different technologies, and the challenges the proposed HPF faces are discussed.

In this paper, a Silicon On Thin Buried-oxide (SOTB) implementation of a 32-point Discrete Cosine Transform (DCT) is presented. The architecture is based on the fixed-rotation adaptive COordinate Rotation DIgital Computer (CORDIC) algorithm. The SOTB-65 nm process was chosen due to the profound advantages of low-power and high-performance. The core layout contained about 47.2 K gate-count and had the size of about 183 K-µm². The measurement results showed that the highest operating frequency of 62-MHz was achieved at the 1.05-V power supply and consumed about 737-µW and 11.89-pJ/cycle. In the standby mode, the least power consumption of 0.12-nW was achieved at the 0.4-V power supply when the clock-gating technique and −2.5-V reverse back-gate biassing were applied.

The analytic expressions of input-output dynamic parameters of memristor (i.e., state variable, memristance, and output response) with respect to initial phase of sinusoidal input are obtained by using Homotopy Analysis Method (HAM). Furthermore, a new exponent, called Response Time Delay (difference) between the Maximum Values of input and output—RDMV-IO, is proposed to rapidly analyze the memristor input-output dynamics, under different initial phases. Employing RDMV-IO, we further reveal the intrinsic relationship between initial phase and dynamics. The studies are verified by using Mathematica simulations adopting nonlinear dopant drift memristor model coupled with window function.

A novel, very low profile and ultra-thin inverted ‘E’ shaped monopole antenna for WLAN/WiMAX applications in the laptop computer is presented. The thickness of the antenna is only 0.2 mm and is designed using only a pure copper strip of size 20 × 6 mm². The innovation of the design is miniaturized size and wider impedance bandwidth in dual band operation using two monopole radiating strips namely RS (inverted J) and PQ (inverted Z) along with open ended vertical tuning stub of size 4.5 × 1 mm². The measured impedance bandwidth spanned as 11.24% (2.35–2.63) GHz in a lower band (F_l) and 18.78% (4.92–5.94) GHz in the upper band (F_u) for VSWR < 2 and covers 2.4/5.2/5.8 GHz WLAN and 5.5 GHz WiMAX bands. The presented antenna has proved excellent radiation performance, including nearly omnidirectional patterns, a stable gain of around 4 dBi and an excellent efficiency of around 90% in F_l and F_u bands. This confirms the applicability for WLAN/WiMAX applications in the prominent ultra-thin laptop computers.

This paper presents a 0.4-V continuous-time delta-sigma modulator for high-quality power-efficient audio applications. A new ultra-low voltage amplifier for high linearity and low power consumption is proposed by exploring class-AB topology with a novel local common-mode-feedback loop. A low V_T self-body-biased PMOS switch is employed in feedback digital-to-analog converter to improve the linearity performance against PVT-induced on resistance variation, which avoids clock boosting that may harm long-term reliability. A simple and robust non-overlapping clock generation circuit is proposed for high SNDR performance of modulator at 0.4-V or below. Fabricated in a 130-nm CMOS process, the modulator achieves 90.2 dB signal-to-noise-plus-distortion ratio (SNDR) with 0.2 pJ/step Figure-of-Merit (FoM) over a 20-kHz signal bandwidth, outperforming the reported audio delta-sigma modulators operating at 0.5-V or below. Furthermore, the modulator can operate with a supply down to 0.34-V while achieving an 86.1 dB SNDR at 0.17 pJ/step.

This paper presents a low-power high-precision sigma-delta analog-to-digital converter (ADC) mainly used for DC measurement, especially in applications with high input impedance. A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. Furthermore, it also improves noise performance in the first integrator. The 1.17 mm² chip is fabricated in a standard 65 nm CMOS process. Measurement results show that the ADC achieves 20-bit resolution, 10 ppm INL and a 0.6 µV offset, while consuming 860 µW from 3.3 V supply.

In this paper we propose an architecture of the anti-jamming circuit in high precision GNSS receiver chip base on the frequency-time domain solution, at most, the jamming signals of 12 frequency points can be detected and eliminated at the same time. In addition, an jamming detection strategy based on short-long time FFT is proposed and a circuit of FFT engine with low cost is designed to reduce the area and dynamic power of the GNSS receiver chip. Finally, we complete the VLSI design by using 55 nm digital process, the circuit area is 0.082 mm², the average dynamic power is 0.943 mW. The implementation results prove the effectiveness of the proposed anti-jamming circuit.

A flexible and multipurpose Single Event Effects (SEEs) testing system was developed for evaluating the reliability of nanoscale Very Large Scale Integrated Circuit (VLSI). The accurate detection, comparation and classification of latch-up, upset, and functional interrupt were achieved. In host PC part, two customized software systems were developed, including the Procise for maximal resources occupation and a C^# based visual control interface for real-time communication. For hardware, a motherboard-daughterboard system guaranteed testing performance and kept its compatibility throughout testing. The fault injection and ¹⁸¹Ta³¹⁺ irradiation results indicated the validity of proposed measurements and the stability of hardware operation. Importantly, the high anti-irradiation performance of device was also verified.

This article investigates the radiation properties of the wireless devices in nuclear power plants (NPPs) and proposes a new exclusion zone (EZ) with NPP indoor environment. The indoor EZs were affected by the multiple reflections, standing wave, and diffraction depending on the indoor geometry. To accurately analyze the variations between the indoor EZ and free-space EZ, multiple reflection ray tracing, modal analysis of a cylindrical coordinate, and measurements are performed. The results demonstrate that the proposed indoor EZ applied to the NPP environment is more practical and suitable than the EZ in free-space.

A 6-bit digitally controlled active phase shifter is implemented in 0.13-µm SiGe BiCMOS process for 6–18 GHz phased-arrays. An input passive balun with center open stub is applied to split the single input to differential and achieve high amplitude/phase balance. A degenerated-Q quadrature all-pass filter (QAF) is used to generate two orthogonal vectors with high I/Q accuracy over a wide bandwidth and a main digital-to-analog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution. In addition, a calibration DAC is adopted to compensate the amplitude variations and the phase error introduced by balun and QAF. Consequently, high resolution along with low gain/phase error can be achieved. The phase shifter has achieved root mean square (RMS) phase error of <4.36°, and RMS gain error of <1.04 dB for all 6-bit phase states at 6–18 GHz. The power gain ranges from 0.95 dB at 6 GHz to −1.85 dB at 18 GHz. Input 1 dB compression point (IP_−1dB) is 5.4–8 dBm at 6–18 GHz for 0°-phase state. The total power consumption is 74.4 mW, and the overall chip size is 1.8 × 1.3 mm².