Nowadays, data centers are critical infrastructure for the information industry. Thermal security is one of the most concerning problems of the data center efficiently providing service. The temperature prediction method is an effective way, which overcomes the lagging of the feedback control and rewards a high prediction accuracy. While the current LSTM based prediction methods are limited in accuracy and restricted in scalability due to the lack of knowledge of physical properties and consideration of time constant differences of features. To address this, we propose a data center temperature prediction model with two-segment LSTM for prediction separately for IT equipment load and other heat-related variables with different time constants. The model takes into account the physical properties of the equipment and achieves higher prediction accuracy. The experimental results show that the prediction accuracy of our method is 27.27% higher than the state-of-art single segment LSTM method.

For capacitive-isolated gate drivers, the pulse width distortion (PWD) and common mode transient immunity (CMTI) are vital factors to evaluate its performance. In this paper, an envelope detection circuit and a dV/dt noise canceling circuit of capacitive-isolated gate drivers is designed based on X-FAB 0.35µm CMOS process. With these structures, this gate driver alleviates PWD and improve CMTI. Spectre simulation results show that the gate driver achieves 200kV/µs CMTI with 50ns propagation delay and maximum 7.4ns PWD. Besides, it has better robustness to fabrication process and temperature variation than conventional methods.

In this paper, we propose a software-based simulator and an optimized hardware implementation of the CORDIC algorithm. The number of iterations and the bit width are selected by their relationship calculated by the simulator to satisfy precision requirement. In the proposed hardware implementation, the addition and subtraction operations share the hardware resources. The two’s complement is calculated in two steps: inverting and adding one. The adding one operation is integrated in the addition component of the iteration. In addition, a 3:2 compressor is used to reduce the number of adders, and a carry look-ahead adder is used to reduce the critical path. The synthesized results show that when compared with state-of-the-art designs, our method reduces the area by 53.79% and the delay by 58.97% while maintaining the same precision.

In this study, a vasomotion quantification method using a photoplethysmography prototype, which performs near-infrared spectroscopy combined with green light, is proposed. This structure suppresses the motion artifact and is held by eyeglasses at the back of the ear; this helps improve the integrity of the measured relative concentration changes of the total hemoglobin and pulse wave amplitude during exercise with and without the presence of wind impacting the face. We established a microcirculatory windkessel model including arteriovenous anastomoses estimated from blood flow changes in the depth direction that were acquired using three wavelengths of light and reproduced the vasomotion on a computer. The values predicted by the model were in good agreement with the measured values. The extracted vasomotion can be used to understand autonomic control by the central nervous system.

This paper presents a high-precision bandgap voltage reference (BGR) with a double-ended current trimming technique. A high-order curvature compensation method is adopted to compensate for the nonlinearity of V_BE. The proposed trimming technique using the one-time programmable (OTP) programming cancels the errors caused by process variation and enables bulk production, which achieves a best TC of 2.2ppm/°C from -40°C to 125°C. The proposed BGR is fabricated in a 0.18-um BCD process with an active area of 0.329mm². The line sensitivity is 0.18%/V operating from 2.9V to 3.6V.

This paper presents a high reliability low dropout linear regulator with high voltage tolerance, which uses an open loop structure and is applied to the feedforward response portion of the power tube gate to enhance the transient response of the LDO. The proposed LDO is simulated using a 0.18um DTI isolated BCD process with a 3.3V-14V supply voltage, a maximum input voltage of 40V and an adjustable output voltage of 3.1V/5V. The line regulation is 0.086% at 40V high voltage input and the supply voltage rejection ratio of the circuit can be maintained at around 60dB.

A sub-harmonic mixer for the 220-325GHz band was developed using a SiC platform for the first time. An anti-parallel Fermi-level managed barrier diode pair was monolithically integrated with waveguide couplers and filters on an epi-layer transferred SiC substrate. The sub-harmonic mixer chip was assembled in a waveguide-input package with a broadband transimpedance amplifier. The lowest obtained noise equivalent power was as low as 5×10^-19W/Hz for a signal frequency of 300GHz and local oscillator (LO) frequency of 145GHz with an LO power of only 100µW.

Owing to the large area and power consumption of traditional physically unclonable function (PUF) circuits, they are susceptible to interference from environmental factors. A compact PUF circuit design scheme is proposed by analyzing the circuit structure and sub-threshold leakage current deviation characteristics of a bistable PUF. First, the current-voltage sensitive characteristics of a transistor in the sub-threshold operating region are utilized. Next, to improve the output response speed and the uniqueness of the characteristic information of the PUF circuit, the proposed PUF circuit is designed which combines with the positive feedback and RS latch characteristics. Finally, simulation results based on the TSMC 65nm CMOS process show that the PUF has good uniqueness, randomness, and reliability. The cell layout area, the bit error rate (BER) in the worst case, and the energy consumption are 0.177µm², 2.8%, and 8.976fJ/bit respectively.

This paper presents Hexa-SSD, a novel SSD-internal DRAM management scheme that allows the SSD capacity to scale beyond the slow growth of capacitors. Hexa-SSD judiciously manages the dirty memory footprint within the SSD-internal buffer by using a low-overhead data reordering scheme on the deep queues available in today’s storage interfaces. In doing so, our design guarantees crash consistency while using a fraction of the capacitors compared to the state-of-the-art designs. We implement our design in FEMU and demonstrate that Hexa-SSD delivers up to 1.4× higher IOPS and up to 49% less write amplification compared to the existing scheme under power constraints.

Angle-sensitive pixel (ASP) made of silicon-on-insulator (SOI) p-n junction photodiode (PD) and aluminum (Al) line-and-space (L/S) grating gate electrode is proposed, and the incident angle dependence of spectroscopic quantum efficiency (QE) in visible light range are evaluated experimentally. Good agreement between measured peak wavelengths and theoretical ones was successfully obtained for various grating periods and two linearly-polarized lights. The proposed ASP would contribute to the advanced imaging with incident angle information.