A capacitance multiplier with large multiplication factor, increased accuracy, and class AB operation is presented. The multiplier is an impedance mode implementation consisting of a Flipped Voltage Follower based on Operational Transconductance Amplifiers (OTA). This gives the possibility to offer rail-to-rail operation and class AB operation to drive demanding loads depending on the application. In addition, one of the OTAs is designed to offer a transconductance gain based on passive resistors and achieve increased accuracy in the multiplication factor by means of proper layout techniques. The circuit was implemented in a 0.5µm technology and has multiplication factors of 10, 100, 1k and 10k, a power dissipation of 0.56mW and a silicon area of 0.059mm2. Simulation and experimental results of the multiplier demonstrate the proper operation.
In this paper, a low-latency asynchronous arbiter based on standard cell library was proposed. The circuit which was implemented based on standard cell library, could be synthesized by mainstream EDA tools and suitable for being part of large-scale digital designs. With the employment of parallel processing techniques, Quick Request Forward and Quick Acknowledgement Release, which were able to reduce the release time by shortening the long feedback delay, the proposed asynchronous arbiter could provide a low latency. Post-layout simulations showed that the cycle time of the proposed arbiter was 7.3-40% better than existing arbiters in terms of latency in a simple communication model and 35.26-81.84% better in a complex communication model. In addition, the advantage became distinct as N increased.
This paper proposes a MOSFET-based all-digital temperature sensor fabricated in a standard 55-nm CMOS process. The temperature sensing elements of the sensor are composed of ring oscillators, which convert temperature information into frequency information. The frequency ratio’s proportional to absolute temperature (PTAT) feature is generated by using two separate frequency oscillators with varied temperature sensitivity. The frequency-to-digital converter (FDC) converts frequency information into digital representation without introducing any overhead reference clock. A die area of 1915µm2 is occupied, owing to the all-digital architecture. After two-point calibration, the proposed sensor achieves an error of -0.4°C∼+0.6°C throughout a temperature range of -40°C∼125°C. With the help of class-adjustable oscillators, the sensor can function in a wide supply voltage range from 0.5V to 1.2V. It obtains a resolution of 0.166°C at room temperature with a dissipation of 2.5µW.
To improve the reliability of the variable flux reluctance machines (VFRMs) in the early stages, this letter proposes a novel fault feature for armature winding short-circuit (AWSC) fault in four-phase VFRMs. First, the harmonic characteristics of field induced voltage are researched theoretically in detail under normal and AWSC conditions. Then, a diagnosis method based on the harmonics of the field induced voltage is proposed and analyzed by simulation. Finally, related experiments are conducted to verify the proposed method. The proposed diagnosis method is simple and feasible, which can realize reliable protection of the power generation system for safe operation.
This paper proposed three reverse voltage protection circuits for the power MOSFETs in low dropout power applications. Power devices are vulnerable to instantaneous current overshoot when the input voltage is lower than the output voltage. Compared with conventional solutions using diode for reverse current block, the proposed three structures consume fewer voltage drop during normal operation. The first design is suitable for applications with wide output ranges but requires the largest die area. The other two solutions are for applications with low output voltages, and are characterized with effective area arrangement and dead-zone free control, respectively. The proposed three protection structures require 126.2%, 12.25% and 43.05% extra die area of the power devices, respectively.
This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ΔΣ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves -85.94dBc/Hz@100kHz and -109.18dBc/Hz@1MHz in fractional-N mode while consuming 1.6mW under a 0.7V voltage supply.
A new quasi-Z-source high step-up dc-dc converter is proposed in this letter. Compared with a conventional quasi-Z-source dc-dc converter, the proposed converter features low voltage ripple at the output, the use of a common source switch, and low stress on circuit elements. The advantages including low EMI, free of high side driver, and reduction of cost has been expected. The new topology named as a low-side-drive Quasi-Z-source boost converter (LQZC) consists of a flying capacitor (CF), the QZ, two diodes and a N-channel switch. About 1/5 reduction of the output ripple was verified by the PSIM simulation when the input voltage is 48V at a duty ratio of 0.1.
This paper proposes a computation-array-centered dataflow, which adjusts the convolution with different kernel sizes to a unified computing manner and reduces the dimension of computation array from 2D to 1D, so as to maximize the utilization of the computation elements offered by the accelerator. Furthermore, a single unit multiple data (SUMD) strategy is proposed to effectively alleviate the mismatch between the quantized data and the hardware resources with fixed bit width on FPGA. As a case study, an 8-bit MobileNetV2 model has been implemented on the low-cost ZYNQ XC7Z020 FPGA, whose FPS/DSP and GOPS/DSP achieve upto 0.55 and 0.35 respectively.