A 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS is presented. To diminish the fluctuation of common-mode voltage (VCM) and switching energy during conversion, a VCM-stable switching scheme is adopted without increasing the design complexity to VCM buffers. Moreover, tri-switch sampling is employed in this design. Together with the binary-scaled recombination weighting (BSRW) method, it cancels the gain error and non-linearity caused by the parasitic input capacitor of comparators. The measurement results show that the reported ADC achieves an ENOB of 9.3 bits sampled at 120MS/s. The worst differential non-linearity (DNL) and integrated non-linearity (INL) are both below 0.5 LSB. The proposed ADC consumes 1.08-mW power, resulting in a figure of merit (FoM) of 14.3fJ/Conv.-step.
A method for designing a broadband high-efficiency power amplifier (PA) based on a novel loop-shaped filter matching structure is proposed in this paper. By combining a power amplifier matching circuit and a loop-shaped filter structure, a broadband high-efficiency PA based on a new harmonic matching structure is realized. The novel loop-shaped filter can control the second and third harmonics in a wide frequency range and has a specific control effect on higher-order harmonics, which can further expand the bandwidth of class-F PA and improve efficiency. To verify its feasibility, a power amplifier with a bandwidth of 1.6GHz-3.4GHz, a saturated output power greater than 41dBm, a drain efficiency of 65%-72% with a gain greater than 10dB is designed and fabricated using GaN HEMT CGH40010F transistor.
In this letter, a new miniaturized dual-band frequency selective surface (FSS) with second-order frequency responses at each band is presented. The proposed structure is designed by cascading three metallic layers that are separated by two thin dielectric substrates. The proposed FSS composed of resonant and non-resonant elements implements two independently controllable pass-bands performance. An equivalent circuit model of the structure is provided to demonstrate the filtering mechanism. The proposed FSS provides stable filtering characteristics and sharp roll-off characteristics centered at X- and Ku-band, respectively. In addition, the proposed FSS exhibits highly stable frequency responses for EM waves of different polarizations and incident angles. A prototype of the FSS was fabricated and measured, the measured results have a good agreement with the simulated ones, which verifies the excellent performance of the proposed new dual-band FSS.
A novel compact 4-way ultra-wideband short pulse power divider (PD) based on coaxial waveguide is proposed in this paper. A nylon conical shell is inserted to replace the original transformer oil with an air block at the resonant place of PD to widen the working bandwidth. The junction of all inner conductors is smoothed to increase the fidelity and power capacity. The proposed PD is fabricated and tested. The results show that return loss is better than 12 dBfrom 191MHz to 1.33GHz. The amplitude loss is less than 10% and fidelity is more than 0.95 when input by impulse with full width at half maximum (FWHM) of 1.24ns.
The recent progress of in-vehicle communication networks has been highlighted by the intensive investigation of optical packet communication systems using a modulation and detection device. This paper proposes a burst-mode driver circuit with an on-chip bias switch to achieve a stable and quick response in bias switching operation. The proposed circuit comprises a driver core and two types of bias circuits. Moreover, the proposed circuit changes output bias voltages using a MOS transistor as a switch. To verify the operating principle, we design the proposed circuit using a high-voltage tolerant 65-nm CMOS technology and obtain the post-layout simulations and measurement results. As a result, we achieve quick bias switching operation with 90% faster response time than the conventional one.
This paper proposes a flat bottom driving method for a switched reluctance motor (SRM) by using a full-bridge power converter. Based on a ring structure, an SRM is able to be driven by a full-bridge inverter. With the proposed driving topology, by adding harmonics in the sinusoidal current waveform from the space vector PWM (SVPWM) driving method, the flat bottom current waveform can be generated for driving an SRM. According to the theoretical analysis and calculation, the flat bottom method reduces the copper loss, compared to the SVPWM driving method. The proposed driving topology and flat bottom method are tested by simulation and experimental system, of which the results are compared to that of the SVPWM driving method. The comparison shows that the flat bottom driving method contributes to the reduction of SRM copper loss, and the simulated results match the experimental results well.