This paper presents a novel modeling and analysis of inter-symbol interference (ISI)jitter in serial data channels either between chips or on chip. The simulation results show that ISI jitter is dependent on pole location, settling time, and damping ratio of the data serial channel. Based on the proposed ISI jitter model, the effect of the ISI jitter on other jitter components is illustrated along with realistic simulation results.
In order to replace existing TDM-PON (TDM-Passive Optical Network) systems by new PON (10G-PON) systems providing 10Gbit/s access in a flexible manner, it is necessary to realize loss budgets that are not less than those of existing PON systems. In this paper, we propose a new 10Gbit/s APD burst-mode receiver, which attains the sensitivity of -24.8dBm and the dynamic range of 17.8dB. When forward error correction (FEC) is employed, the corresponding values are -29.8dBm and 22.8dB; the resulting loss budget of 29dB satisfies the requirement for new PON systems.
A novel protocol for point-to-point data transfer services on a wireless network is proposed. The protocol is designed using cross-layer design methodology, which makes the time from the start of connection setup to the start of data transfer 200 times shorter and the maximum throughput up to 1.4 times higher than those of the conventional WLAN. It also provides robust connection under degradation of signal quality.
A compact but accurate HSPICE macromodel for single-bit resistive RAM (ReRAM) is proposed in this paper. This compact macromodel uses the minimum number of circuit elements to improve the HSPICE simulation speed. And, the macromodel is verified to show very good agreement with the measurements due to voltage-controlled resistors used as the SET and RESET resistors in the macromodel describing well the complicated current-voltage relationship of the ReRAM. An extended version of the macromodel is also proposed and verified for multi-bit ReRAM, where its SET resistance and RESET voltage can vary according to the SET pulse width applied to the ReRAM.
This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.