This paper proposes a new scan-based BIST scheme that implements weighted random pattern testing by loading different scan input data into scan chains with proper probabilities. These scan input data include previous scan values into the scan chains, pseudorandom data generated by test pattern generator, test responses collected by the scan chains, and the complement of test responses. Due to increasing the correlation among adjacent test stimulus bits, the proposed method decreases the switching activity during scan shift. Meanwhile our method applies the four kinds of test data with different probabilities to maximize test effectiveness. A greedy procedure is proposed to select the proper probabilities that the four kinds of data are selected for each scan chain. When comparing with an existing method called LT-RTPG, experimental results for larger benchmark circuits of ISCSAS89 show that the proposed method can significantly reduce shift test power while providing higher fault coverage.
G4-FET has attracted attention as an emerging device for the future generations of semiconductor industry. This paper is intended to propose a model representing the characteristics of G4-FET device in order to perform circuit simulations. The modeling approach is established upon the neuro-fuzzy technique whose main strength is that they are universal approximators with the ability to solicit interpretable IF-THEN rules. The accuracy of the proposed model is verified by HSPICE circuit simulations.
The Multilevel Topologies are showed as the next generation of High Power Amplifiers and Sound Quality. This new topology has new components and therefore presents new voltage and distortion errors. One of these new elements is the Clamp-Diodes that connect the neutral-point of DC-Link to Output. These Clamp-Diodes present a Reverse Recovery Time (trr) and their distorting effects cause signal and quality losses and EMI problems. These phenomena are introduced, modeled, and evaluated to discuss the importance of the involvement of the Recovery Reverse Time value in the Multilevel Power Amplifiers performance.
Photovoltaic generation systems and power line communication systems radiate EM-waves below 30MHz. In this situation, measurement sites for the EM-waves are required. However, evaluation methods of the site below 30MHz are not established yet. In this paper, we measure the magnetic behavior below 30MHz in a OATS (Open Area Test Site), and also simulate with a moment method. As the results, the deviation between the measurement and calculation data became within 2.5dB. Therefore, we confirm that this paper’s method of measurement can be used to evaluate the measurement site in below 30MHz.
The spatial polarization characteristic of radar antenna is modeled in this paper. And based on it, a novel polarization estimation method of incoming wave signal is proposed. It is indicated that co-polarized component and cross-polarized component of antenna satisfy even-odd symmetry property, respectively. This conclusion is confirmed by electromagnetic computation and real test data. Our method does not need auxiliary orthogonal polarized antenna. The polarization can be estimated by using only received signal power. The accuracy of measurement method is guaranteed and the realization complexity is reduced. Simulation experiment proved the availability of the method.
In this article, emerging new semiconductor non-volatile memories are reviewed. We are reaching the integration limit of Flash memories and new types of memories replacing Flash have been actively proposed. Each type of memory is briefly introduced and the possibility of replacing Flash is discussed. FeRAMs, MRAMs, and PCRAMs are already in production and the physics behind the operations and reliabilities are well understood. ReRAMs are now approaching to practical use. However, the operation mechanisms of the other memories have not been understood perfectly. Therefore, it is not fruitful to compare the superiority of each technology at this moment because some innovative idea might enhance a specific technology that happened from time to time.
Molecular transistors can play a very important role in the design and fabrication of complex logic functions inside chips. In this paper, we present an SPICE model for simulating molecular transistors for the first time. We also illustrate a novel hybrid architecture in which n-type transistors are carbon nanotube and p-type ones use benzene rings. We have achieved a significant improvement in terms of power-delay product, area and average leakage power in comparison with the pure carbon nanotube design.