IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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Volume 1, Issue 9
Displaying 1-6 of 6 articles from this issue
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LETTER
  • Real-time three-dimensional video image composition by depth information
    Masahiro Kawakita, Keigo Iizuka, Tahito Aida, Taiichirou Kurita, Hiros ...
    2004 Volume 1 Issue 9 Pages 237-242
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.237
    JOURNAL FREE ACCESS
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    We have developed a system of compositing three-dimensional (3D) video images based on the depth information of the objects. The system consists of the Axi-Vision Camera that can measure object distance in real time and an arithmetic image processor that can synthesize video images according to the depth information. The paper demonstrates how to three-dimensionally synthesize such a scene as an array of computer-generated characters moving around a standing person in real time. The feasibility of using such a signal processor to create realistic TV programs in a broadcasting station has been studied.
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  • Fabrication of JFET device on Si (111) for sensor interface array circuit
    Yoshiko Kato, Takashi Hashimoto, Liew Yoke Ching, Hidekuni Takao, Kazu ...
    2004 Volume 1 Issue 9 Pages 243-247
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.243
    JOURNAL FREE ACCESS
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    In this study, single-sided gate JFET structure on Si (111) has been proposed and investigated for array circuit. The performance of the single-sided gate JFET can be optimized by simulation, and has sufficient performance as sensor interface device. The noise level of the (111) JFET at low frequency was about 1/50 of that of a (111) n-MOSFET, and 1/25 of that of a (100) n-MOSFET. It has been experimentally confirmed that single-sided gate JFET is a suitable device as sensor interface on Si (111), possessing large interface states.
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  • Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata
    Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
    2004 Volume 1 Issue 9 Pages 248-252
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.248
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    We designed a special CMOS circuit for reaction-diffusion computers that accepts optical inputs in parallel and generates excitable spatial waves on a chip surface. We demonstrated the spatiotemporal properties of the proposed circuits by fabricated LSIs.
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  • Low temperature formation of β-FeSi2 polycrystalline microstructure by pulsed laser deposition and thermal annealing
    Hiroharu Sugawara, Shingo Nakamura, Masayuki Oouchi, Yui Kumura, Taken ...
    2004 Volume 1 Issue 9 Pages 253-257
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.253
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    β-FeSi2 polycrystalline microstructure was successfully formed at exceptionally low temperature in the form of droplet with room temperature pulsed laser deposition and post-annealing below 350°C employed. Evidence of the β-phase formation was obtained through microscopic Raman spectroscopy and TEM analysis. The low temperature nature may originate from formation of intermediate amorphous phase possibly provided by quick heat removal from Fe-Si melts generated by laser ablation. This low temperature scheme offers an alternative method of producing polycrystalline β-FeSi2 without higher temperature processes, which could be beneficially compatible with the standard Si device fabrication processes.
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  • Finding Steiner trees with degree 1 terminal nodes
    Hector Cancela, Franco Robledo, Gerardo Rubino
    2004 Volume 1 Issue 9 Pages 258-262
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.258
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    We consider in this work a variant of the Steiner Problem in Graphs (SPG) with the additional restriction that terminal nodes must have degree 1. We customize the Greedy Randomized Adaptive Search Procedure (GRASP) metaheuristic, testing its performance on a large problem set obtained by modifying 182 SPG instances from the SteinLib repository. The GRASP obtained good results, with low average gaps with respect to known lower bounds in most of the problem classes, and attaining the optimum in 44 cases (24% of the problem set).
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  • The sprint process of Al interconnects with low-temperature PVD via filling
    Takashi Yoda, Hirokazu Ezawa, Kaori Tsutsumi, Makoto Honda
    2004 Volume 1 Issue 9 Pages 263-268
    Published: 2004
    Released on J-STAGE: August 10, 2004
    DOIhttps://doi.org/10.1587/elex.1.263
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    For multilevel interconnects of LSI memory devices, the Al sprint process using the two-step cold/hot Al PVD at less than 400°C is a realistic solution to reduction of the process cost. The process windows of via filling were investigated for via holes of 0.22µm to 0.16µm. Based on the assumption that Al diffusion decides filling capability, temperature and thickness of the cold Al liner PVD and deposition time of the hot Al PVD were optimized, resulting in complete filling of 0.16µm via holes. We have confirmed the viability of the Al PVD via filling for less than 110nm device generations.
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