In this paper, we present two-way and four-way power dividers that operate in wideband over K-band. To maximize the integrability with other circuit blocks, the power dividers are designed in a purely digital CMOS technology without any RF back-end-of-line process. We discuss a design issue arising from the high loss of transmission lines in the digital process. A capacitor-loaded Wilkinson topology is adopted for a compact size. The proposed dividers are implemented in a 0.13-µm digital CMOS process with automatic dummy metal fills. We also analyze the effect of the dummy fills on the power divider performance, showing good agreement with measured results.

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This paper presents the design of a 6-bit active digital phase shifter in 0.18-µm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5GHz. The average voltage gain ranges from 1.7dB at 2.4GHz to -0.14dB at 5GHz. Input P1dB is typically 1.3±0.9dBm at 3.5GHz for overall phase states.

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In this paper, we propose memory reduction methods for IEEE 802.16e mobile station. Proposed methods are modulation encoder and decoder for uplink allocation, FIFO sharing architecture in downlink synchronizer and replacing frame memory for received signal storing with memory for preamble and FIFO for burst data. Comparison results show that the proposed methods reduce the memory size about 74.5%, 32.2% and 85.2% compared with conventional methods, respectively.

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In this paper, we develop an approach to allow the cognitive radio to operate in the presence of the licensed user using bio-inspired method called particle swarm optimization. This method is invoked to solve the constrained nonlinear optimization problem for the minimum power transmission and minimum bit error rate in order to reach to maximum capacity. In addition, the received interferences at primary users remain below a specific threshold level as well as the secondary users are guaranteed with their quality of service. We reveal the modulation index in the optimization procedure. A numerical study is performed to show the convergence behavior of the proposed bio-inspired algorithm in a non-stationary environment with a dynamic cost function.

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A high data rate wireless transmission scheme, utilizing the Medical Implant Communications Service (MICS) band for implantable medical devices (IMD) is proposed. An orthogonal frequency division multiplexing (OFDM)-based multicarrier scheme is used to overcome the data rate limitation caused by the narrow bandwidth. By optimizing subcarrier allocation, inverse fast Fourier transform (IFFT) architecture and sidelobe suppression techniques, the proposed scheme utilizes multiple MICS channels simultaneously, satisfying the MICS mask specification. Simulation results show that this scheme can support a maximum data rate of 4.86Mbps, which is more than ten times faster than the existing system.

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We study the iterative soft interference cancellation-minimum mean square error filtering (ISIC-MMSE) detector with estimated channel state information (CSI) for bit-interleaved coded modulation (BICM) spatial multiplexing multiple input multiple output (SM-MIMO) systems. By considering the channel estimation errors in all detection modules, we propose a modified ISIC-MMSE detector which considerably outperforms the conventional ISIC-MMSE detector in terms of performance and transmission rate with only moderate complexity increase.

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A capacitance deviation-to-time interval converter is presented for interfacing capacitive sensors. It consists of two ramp integrators, two current-tunable Schmitt triggers, and two logic gates. A prototype circuit built using discrete components exhibits a resolution as high as 13bits and a linearity error less than ±0.2% when the output pulse width is counted by a 20MHz clock signal. Its application to a humidity sensor is also presented.

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Visual perceptual degradation is usually introduced during 3D mesh simplification. Some geometric metrics without considering human visual perception and perceptual metrics based on subjective test have been proposed. A new Global Perceptual Structural Degradation metric (GPSD) based on mesh saliency and information theory to evaluate the visual perceptual degradation is proposed in this letter. It can also provide the function of multi-scale evaluation of visual degradation effectively. The accuracy and validity of the proposed metric have been demonstrated through subjective experiment.

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We proposed a novel temperature-compensated, ultra-low-power current reference based on two β-multipliers whose resistors are replaced by nMOS devices operated in the deep triode region. The circuit, designed by a 0.25µm CMOS process, produces an output reference current of 13.7nA at room temperature. Simulated results show that the temperature coefficient of the output is less than 100ppm/°C in the range from -20°C to 80°C and the average power dissipation is 0.9µW.

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We investigate a greedy policy for delay-optimal scheduling in broadband wireless networks using relay stations (RS). The key idea behind the policy is that users should greedily exploit opportunism from time varying channels, while the basestation should prioritize balancing queues at RS. A fluid model is presented to show that such policy is optimal in the fluid regime. By simulation we show that the proposed scheme reduces mean delay by up to 73% compared to backpressure algorithm.

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Power noise waveforms of a 32-bit microprocessor were on-chip measured in a 90-nm CMOS technology. A dedicated measurement system combines an embedded programming environment and a measurement flow that ensures acquisition of noise waveforms during designated arithmetic operation. Power noise exhibits clear relation with the contents of computation, where the magnitude of power noise reflects the occupancy ratio of computing resources of a microprocessor. The level of correlation is shown to be different among static and dynamic portions of power noise. It is concluded that practical power noise analysis requires the higher-level abstraction of a large-scale integrated digital system.

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This paper introduces a new technique for reducing the body effect on the channel on-resistance of analog switches. In this technique, the gate of bootstrapped sampling switch tracks the input signal with a variable voltage function. Rail-to-rail performance of proposed switch makes it suitable for low voltage applications. The simulation results show that the proposed technique can significantly improve the dynamic performance of a sample-and-hold circuit.

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